Expert I/O offers system verification component for Serial ATA
Dylan McGrath, EE Times
(03/17/2006 1:55 PM EST)
SAN FRANCISCO — Design and verification service provider Expert I/O is now offering a system verification component (SVC) specifically designed for thorough verification of Serial ATA port multipliers, port selector ASICs and FPGAs using both random and directed simulation.
According to Expert I/O (Simi Valley, Calif.), the component, SATA PM/PS SVC, is constructed using a layered approach so that each layer interface can be used to speed up construction of directed tests. The SVC supports constrained randomization parameters throughout the layers to aid in coverage during randomized testing, according to the company.
(03/17/2006 1:55 PM EST)
SAN FRANCISCO — Design and verification service provider Expert I/O is now offering a system verification component (SVC) specifically designed for thorough verification of Serial ATA port multipliers, port selector ASICs and FPGAs using both random and directed simulation.
According to Expert I/O (Simi Valley, Calif.), the component, SATA PM/PS SVC, is constructed using a layered approach so that each layer interface can be used to speed up construction of directed tests. The SVC supports constrained randomization parameters throughout the layers to aid in coverage during randomized testing, according to the company.
To read the full article, click here
Related Semiconductor IP
- SATA Controller IP Core
- Verification IP for SATA
- Serial ATA (SATA) PHY Transceiver IP
- SATA Verification IP
- SATA Synthesizable Transactor
Related News
- K-Micro Licenses CEVA'S 90nm 3.0Gbps Serial ATA Technology to Enable Topaz Sub-System for Storage Applications
- JMicron Technology Corp Develops Serial ATA II (3.0 Gpbs) PHY Core on UMC's 90nm G and 90nm SP Processes
- New Serial ATA Host Controller from Silicon Image Enables eSATA Connectivity for PC and CE Applications
- Wipro-NewLogic announces availability of its Serial ATA series of Intellectual Property Cores
Latest News
- Weebit Nano announces A$80.0 million Placement
- Joya Design Takes Neuromorphic Chip from Design to Device with First Innatera-Powered Consumer Audio Product at AWE China
- Arm expands compute platform to silicon products in historic company first
- Synopsys Supports New Arm AGI CPU with Full-Stack Design Solutions
- Altera and Arm Collaborate to Deliver Efficient, Programmable Solutions for AI Data Centers