Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with releases for core DMA Engines in RISC-V® & ARM® Systems and Peripherals to Memory Applications
GLEN ROCK, New Jersey, January 14, 2024 – Digital Blocks, a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA developers, offers DMA Controller Verilog IP Core offerings targeting the following system requirements:
- RISC-V® & ARM® Systems requiring a core scatter-gather DMA Engine for AXI4 Memory to/from Memory data transfers
- Systems with streaming data requiring transfer to/from AXI4 Memory and Network Interfaces with AXI4-Stream Interface.
Digital Blocks DMA Controller IP Core family members contain feature-rich, system integration-level features. Current DMA Controllers are as follows:
| DMA Controller Engines |
| AXI4 Multi-Channel DMA Controller, 1-16 Channels, Scatter-Gather, high performance, many user feature-rich, system integration-level options |
| AHB5 Multi-Channel DMA Controller – targets latest AHB Interconnect |
| AXI4-Stream to AXI4 Memory driven by DMA Controller |
| AXI4 Memory to AXI4-Stream driven by DMA Controller |
| UDP/IP Hardware Stack with DMA Controller |
| DMA Controller with Interfaces to PCIe |
Price and Availability
The Digital Blocks DMA Controller IP Core family is available in synthesizable Verilog, along with a comprehensive simulation test suite, datasheet, and user manual. For further information, product evaluation, or pricing, please go to Digital Blocks at https://www.digitalblocks.com/dma.html
About Digital Blocks
Digital Blocks is a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA developers requiring best-in-class IP for AMBA Peripherals (DMA/I3C/I2C/SPI/eSPI Controllers), TFT LCD/OLED Display Controllers & Processors, 2D Graphics Hardware Accelerator Engines, Video Signal & Image Processing, and Low-Latency UDP/RTP Hardware Protocol Stacks.
Digital Blocks designs silicon-proven IP cores for technology systems companies, reducing customer’s development costs and significantly improving their time-to-volume goals. Digital Blocks is located at 587 Rock Rd, Glen Rock, NJ 07452 (USA). Phone: +1-201-251-1281; Fax: +1- 702-552-1905; Media Contact: info@digitalblocks.com; Sales Inquiries: info@digitalblock.com; On the Web at www.digitalblocks.com
Related Semiconductor IP
- I2C Controller IP – Slave, Parameterized FIFO, Avalon Bus
- I2C Controller IP – Master, Parameterized FIFO, Avalon Bus
- I2C/SMBus Controller IP – Master / Slave, Parameterized FIFO, AXI/AHB/APB/Avalon Buses, SMBus Protocol
- I2C Controller IP- Master / Slave, Parameterized FIFO, Avalon Bus
- I3C Controller IP – I3C / I2C Slave, Configure User Registers, no CPU Host Required
Related News
- Digital Blocks AMBA Peripherals I3C, I2C, eSPI, xSPI Controller IP Core Families Extend Leadership with enhancements containing feature-rich, system-level integration features.
- Digital Blocks Announces the AMBA Multi-Channel DMA Controller IP Core
- Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with targeted applications in DMA Streaming of Video and Data over PCIe or UDP/IP Network Interface.
- DDMA, multi-channel DMA Controller IP core from DCD-SEMI
Latest News
- ZeroPoint Technologies Unveils Groundbreaking Compression Solution to Increase Foundational Model Addressable Memory by 50%
- Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
- AheadComputing Raises $21.5M Seed Round and Introduces Breakthrough Microprocessor Architecture Designed for Next Era of General-Purpose Computing
- Intel’s Altera Unit Nears Sale as Silver Lake Reportedly Leads Talks
- Cadence Reports Fourth Quarter and Fiscal Year 2024 Financial Results