Denali Software Celebrates One Hundredth Chip With DDR Controller IP Product
Databahn Achievement Signifies Industry Milestone in Deployment of DDR Memory Systems
PALO ALTO, Calif. -- Sept. 24, 2007 -- Denali Software, Inc., a world-leading provider of electronic design automation (EDA) software and intellectual property (IP), today announced that its Databahn(TM) DDR memory controller IP has been successfully deployed in 100 chips. The customer of the 100th successful chip was Coherent Logix, Inc., who used Denali's Databahn DDR memory controller IP to meet application-specific performance requirements for their design. The Databahn IP ultimately enabled Coherent Logix engineers to accelerate their time to market and minimize design risk for their product.
"We were pleased with the performance and overall ease of integration of Denali's Databahn memory controllers into our chip design," said Michael Solka, vice president of engineering at Coherent Logix. "We used Databahn controllers in our design to support our required DDR1 and DDR2 memory interfaces. During the RTL coding and integration phase, we found that Denali's IP was easy-to-use and to integrate which facilitated our fast design cycle. Today's design specifications necessitate high quality IP and we are pleased with Denali's expertise in their ability to meet these requirements."
DDR DRAM is a key component in many memory subsystems found in a variety of computing, networking and communications manufactured today. With DDR DRAMs achieving speed grades up to 1600 Mbps, high-performance DDR interfaces are a critical variable in overall system performance. To better address these challenges, designers need a high-quality, proven solution consisting of more than the digital DDR memory controllers.
"Today's high-performance SoCs require specialized DDR memory systems that must address several design criteria plus an aggressive time-to-market schedule," said Brian Gardner, vice president of IP products for Denali. "Our Databahn DDR controller has reached a unique silicon-proven benchmark in the industry allowing our customers to make an easier choice to address their application specific performance requirements. We are very content with Coherent Logix first-pass silicon-success with their complex, high-performance SoC."
About Databahn DDR Memory Solutions
With over 250 design wins and 100 chips in silicon, Databahn is the industry leading IP solution for DDR memory systems. Databahn DDR controllers ensure interoperability with all the latest high-speed memory technologies as the configuration process is tightly integrated with Denali's database of memory component specifications, including all the latest SDRAM, DDR1, DDR2, DDR3, GDDR3, and LP-DDR devices from all major memory vendors. Deliverables include: RTL and synthesis scripts, silicon-independent DDR PHY, verification testbench, static timing analysis (STA) scripts, programmable register settings, and documentation. Databahn controllers are compliant with all the latest memory devices, and are silicon-proven in over 27 process nodes. For the latest Databahn DDR memory solutions information, visit: http://www.denali.com/products/dram.
About Denali Software, Inc.
Denali Software, Inc., is a world-leading provider of electronic design automation (EDA) software and intellectual property (IP) for system-on-chip (SoC) design and verification. Denali delivers the industry's most trusted solutions for deploying PCI Express, NAND Flash and DDR DRAM subsystems. Developers use Denali's EDA, IP and services to reduce risk and speed time-to-market for electronic system and chip design. Denali is headquartered in Palo Alto, California and has offices around the world to serve the global electronics industry. More information about Denali, its products and services is available at http://www.denali.com.
Related Semiconductor IP
- Simulation VIP for Ethernet UEC
- CAN-FD Controller
- Bluetooth® Low Energy 6.2 PHY IP with Channel Sounding
- Simulation VIP for UALink
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
Related News
- Arasan Announces immediate availability of its Total IP for Embedded USB2 (eUSB2) with Controller and PHY
- Arasan Announces the industries first MIPI SWI3S Manager IP and Peripheral Controller IP
- DDR PHY Interface Specification to be Unveiled Next Week at MemCon
- ARM, Denali, Intel, Rambus, Samsung, and Synopsys Collaborate on DDR PHY Interface Specification for DDR-DRAM Memory System Design
Latest News
- WAVE-N v2: Chips&Media’s Custom NPU Retains 16-bit FP for Superior Efficiency at High TOPS
- Quintauris releases RT-Europa, the first RISC-V Real-Time Platform for Automotive
- PQShield's PQCryptoLib-Core v1.0.2 Achieves CAVP Certification for a broad set of classical and post-quantum algorithms
- M31 Debuts at ICCAD 2025, Empowering the Next Generation of AI Chips with High-Performance, Low-Power IP
- Perceptia Begins Port of pPLL03 to Samsung 14nm Process Technology