CXL Testing Leverages PCIe Expertise

By Gary Hilson, EETimes (March 29, 2023)

Every open standard needs a robust ecosystem if it is to be widely adopted—and that includes testing and verification capabilities. Just as vendors have rallied around the rapidly evolving Compute Express Link (CXL) specification to announce a variety of products, so have players offering tools to help make sure these products perform reliably and play nice with each other.

Making CXL testing and verification legwork easier is the fact that the interconnect runs on the Peripheral Component Interconnect Express (PCIe) bus standard, which is both ubiquitous and well-understood. PCIe also provides the underlying foundation for the rather mature Non-Volatile Memory Express (NVMe) specification.

While there is a lot of validation involved with CXL for an SSD maker like Phison Electronics, there is nothing that’s substantially divergent from PCIe validation, Phison CTO Sebastien Jean said in an exclusive interview with EE Times.

About 80% of the firmware revolves around NAND management, he said, and then there’s about 20% that is a chunk of code that’s protocol-specific. “From our perspective, it really is just another interface.”

The process of embracing CXL is figuring out what an SSD has to do so it can service memory read and write requests, Jean said.

Once you get past the protocol, it’s all about NAND management, which must be married to CXL in the back end. Servicing PCIe commands involves following a strict order in which commands are processed—typically when they’re received, he said. “But if you’re going through sufficiently complex topology, there are cases where certain commands are allowed to pass others, and those rules are very strict.”

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