CXL Protocol Adds Capabilities over PCIe
By Gary Hilson, EETimes (May 18, 2020)
The Compute Express Link (CXL) protocol is rapidly gaining traction in data centers. It’s an alternate protocol that runs across the standard PCI Express (PCIe). CXL uses a flexible processor port that can auto-negotiate to either the standard PCIe transaction protocol or the alternative CXL transaction protocols. The first generation of the protocol aligns to 32 Gbps PCIe Gen5.
High-performance computational workloads are stressing systems in new ways. System designers are re-thinking their architectures in response. Some of those response include the increasing use of persistent memory, the adoption of purpose-built processors and accelerators, and new approaches to computational storage. Another is CXL.
To read the full article, click here
Related Semiconductor IP
- CXL 4 Verification IP
- VIP for Compute Express Link (CXL)
- CXL 3.0 Controller
- CXL Controller IP
- CXL memory expansion
Related News
- Avery Design Systems Pairs PCIe and NVM Express VIP with Teledyne LeCroy Summit Protocol Exercisers
- PLDA Announces Robust Verification Toolset, Increasing Design Accuracy and Reducing Time-to-Production for Next Generation SoCs with CXL, PCIe 6.0 or Gen-Z Interconnect
- Synopsys DesignWare CXL IP Supports AMBA CXS Protocol Targeting High-Performance Computing SoCs
- PLDA Announces XpressLINK-SOC CXL Controller IP with Support for the AMBA CXS Issue B Protocol
Latest News
- EU DARE Project Is Scrambling to Replace Codasip
- Sofics and Alcyon Photonics Partner to Support Next-Generation Photonic Systems
- QuickLogic Appoints Quantum Leap Solutions as Authorized Sales Representative
- Cadence and NVIDIA Expand Partnership to Reinvent Engineering for the Age of AI and Accelerated Computing
- Cadence and Google Collaborate to Scale AI-Driven Chip Design with ChipStack AI Super Agent on Google Cloud