Research Project for Energy-efficient Risk Management has Started
Kaiserslautern, Oct. 1 2012 - The ESR research project (Energy-efficient simulation acceleration for risk measurement and management) has started with Creonic GmbH as project coordinator.
The precise and significant simulation of risk scenarios is essential for rating current and future portfolios and investments in the financial and insurance sectors. Even large CPU or GPU clusters can have a workload of many hours for such tasks resulting in huge energy consumption for these simulations.
The ESR project is an interdisciplinary cooperation between partners from the sectors of asset management, financial mathematics, and hardware design. The main objective is to make current reconfigurable hardware (field programmable gate arrays, FPGAs) easily applicable for users in finance and insurance markets. In this way a reduction of energy consumption of up to 90% is achievable compared to that of CPU or GPU implementations.
The technical challenge is to keep the high flexibility that is always required because of fast changing product descriptions, models and algorithms while using efficient and therefore dedicated accelerators. During the project the consortium develops a demonstrator for the acceleration of selected algorithms that are relevant for industry. This demonstrator will form the foundation for a commercial platform.
The project consortium consists of:
- Assenagon GmbH, Munich: Asset Management
- Creonic GmbH, Kaiserslautern: Hardware design for FPGAs
- cronologic GmbH & Co KG, Frankfurt: FPGA boards and integration
- Fraunhofer-Institut für Techno- und Wirtschaftsmathematik (ITWM), Kaiserslautern
- Karlsruhe Institute of Technology (KIT): Information processing technologies
- University of Kaiserslautern: Microelectronic systems design
The project is funded by the Federal Ministry of Education and Research and is accompanied by the German Aerospace Center (DLR). The duration of the project is three years.
Website of the ESR project
Related Semiconductor IP
- General use, integer-N 4GHz Hybrid Phase Locked Loop on TSMC 28HPC
- JPEG XL Encoder
- LPDDR6/5X/5 PHY V2 - Intel 18A-P
- ML-KEM Key Encapsulation & ML-DSA Digital Signature Engine
- MIPI SoundWire I3S Peripheral IP
Related News
- SmartDV Releases Portfolio of Verification Intellectual Properties that Support Platform-independent Simulation Acceleration (SimXL)
- ANSYS Simulation Solutions Bolster ARM Energy-Efficient IP For Internet of Things and Cloud Servers
- Aldec unveils Xilinx UltraScale FPGA-based prototyping board enabling Simulation Acceleration and Emulation with the latest release of HES-DVM
- Creonic's Quality Management System Achieves ISO 9001:2015 Certification
Latest News
- Mixel MIPI IP Integrated into Automotive Radar Processors Supporting Safety-critical Applications
- GlobalFoundries and Navitas Semiconductor Partner to Accelerate U.S. GaN Technology and Manufacturing for AI Datacenters and Critical Power Applications
- VLSI EXPERT selects Innatera Spiking Neural Processors to build industry-led neuromorphic talent pool
- SkyWater Technology and Silicon Quantum Computing Team to Advance Hybrid Quantum-Classical Computing
- Dnotitia Revolutionizes AI Storage at SC25: New VDPU Accelerator Delivers Up to 9x Performance Boost