Credo Demonstrates Single-Lane 112G and 56G PAM4 SerDes IP Solutions at TSMC 2017 OIP Ecosystem Forum
Shows Solutions For HyperScale Data Center Connectivity in 100G, 200G and 400G Networks
MILPITAS, CA -- September 13, 2017 -- Credo Semiconductor, a global innovation leader in Serializer-Deserializer (SerDes) technology, today announced it will demonstrate its full offering of advanced SerDes IP at this week's TSMC Technology Symposium, showcasing single-lane 112G PAM4 SerDes solutions.
The wide range of Credo SerDes IP solutions enables ASIC, ASSP, and SoC designers to meet the power and performance requirements of a variety of TSMC advanced processing nodes and supports emerging IEEE standards including 802.3cd/802.3bs/802.3bm which call out 100GBase-DR1, 400GBase-DR4, and 400GBase-FR4.
WHERE:
TSMC Open Innovation Platform Ecosystem Forum
Santa Clara Convention Center
5001 Great America Parkway
Santa Clara, CA 95054
Booth #907
WHEN:
September 13, 2017
8:00 a.m. - 6:30 p.m.
WHAT:
The TSMC OIP Ecosystem Forum brings together TSMC's design ecosystem companies and our customers to share practical, tested solutions to today's design challenges. Success stories that illustrate TSMC's design ecosystem best practices highlight the event.
About Credo Semiconductor
Credo is a leading provider of high performance, mixed-signal semiconductor solutions for the data center, enterprise networking and high-performance computing markets. Credo's advanced Serializer-Deserializer (SerDes) technology delivers the bandwidth scalability and end-to-end signal integrity for next generation platforms requiring single-lane 25G, 50G, and 100G connectivity. The company makes its SerDes available in the form of Intellectual Property (IP) licensing on the most advanced process nodes and with complementary product families focused on extending reach and multiplexing to higher data rates. Credo is headquartered in Milpitas, California and has offices in Shanghai and Hong Kong. For more information: www.credosemi.com
Related Semiconductor IP
- 16Gbps SerDes IP on TSMC 12nm
- 224G SerDes PHY and controller for UALink for AI systems
- Multi-Standard SerDes PHY
- 64G SerDes
- 112G SerDes USR & XSR
Related News
- Credo Demonstrates Single-Lane 112G and 56G PAM-4 SerDes IP at TSMC OIP Forum
- Credo Demonstrates 112G PAM4 SR, 56G PAM4 LR, and 56G NRZ SerDes Technology at DesignCon
- Credo Demonstrates 112G PAM4 and 56G PAM4 SerDes IP Solutions at TSMC 2018 Technology Symposium
- Credo 16-nm 56G PAM-4 SerDes IP Now Available
Latest News
- CAST Releases First Dual LZ4 and Snappy Lossless Data Compression IP Core
- Arteris Wins “AI Engineering Innovation Award” at the 2025 AI Breakthrough Awards
- SEMI Forecasts 69% Growth in Advanced Chipmaking Capacity Through 2028 Due to AI
- eMemory’s NeoFuse OTP Qualifies on TSMC’s N3P Process, Enabling Secure Memory for Advanced AI and HPC Chips
- AIREV and Tenstorrent Unite to Launch Advanced Agentic AI Stack