Configurable DSP cores, 'multicores' unveiled

Configurable DSP cores, 'multicores' unveiled
By Michael Santarini, EE Times
February 22, 1999 (10:11 a.m. EST)
URL: http://www.eetimes.com/story/OEG19990222S0004

Taiwan Semiconductor Manufacturing Corp. (TSMC; Hsin-Chu, Taiwan) and third-party core provider Infinite Technology Corp. (ITC; Richardson, Texas) have teamed up to provide mutual customers with process-specific, designer-configurable DSP cores.

ITC has ported its RADcore technology, a reconfigurable arithmetic data-path architecture, to TSMC's 0.25-micron process. RADcore allows system designers to configure DSP coprocessors for specific applications using preexisting physical libraries. The core will typically hit 350 MHz at 2.5 V and can enable up to 1.4 billion 17 x 17 multiply-accumulate (MAC) operations/second.

The RADcore coprocessor includes a quad MAC architecture. The companies said that customers can use the RADcore technology to create a quad-MAC RADcore that can operate with almost 5 billion overall operations/s. Further, they claim the core is silicon-efficient. Typically, a 5,000-Mops quad-MAC RADcore coprocessor will oc cupy between 2.3 and 3.8 mm2.

Preliminary RADcore Technology design kits with VHDL models for TSMC's 0.25-micron process are expected from ITC in the second quarter. Visit www.infinite-tech.com.

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VLSI Technology Inc. has announced the Vector 3771 multicore, a prevalidated core consisting of VLSI's enhanced ARM7TDMI core and OakDSPCore. The company said the release is the next step in its multicore road map and builds on the Vector 3670 Multicore Development System. The Vector 3771 is designed to address customer time-to-market needs as well as increasing design complexities, the company said.

The multicore provides three levels of reusability. A soft macro offers a flexible solution for customers who wish to modify the physical implementation. A fixed macro block offers a fast time-to-market solution. VLSI Technology also offers the individual building blocks used in the Vector 3771 core and development chip in HDLi for custome rs who wish to modify the system-level implementation.

The Vector 3771 integrates VLSI's enhanced ARM7TDMI and Oak+ DSPCore, clocking at 100 MHz and 80 MHz, respectively, under worst-case conditions. According to the company, low-power techniques were used throughout the design of Vector 3771, suiting it for portable apps. The multicore is a key component in VLSI's recently announced Velocity Rapid Silicon Prototyping System. It is implemented in 0.25-micron process technology for improved performance and is the basis for the Velocity Standard Communication Platform, an integrated wireless-development foundation that addresses such standards as DECT, GSM and CDMA within a single platform.

The core is supported by VLSI's JumpStart development tools, which provide a unified software and hardware development environment. Embedded-system-hardware debug is addressed by VLSI's JTAG-based methodology, and hardware design is supported by Verilog and VHDL behavioral models. VLSI also said that its A RM7TDMI core is now available in 0.2-micron process technology. Visit www.vlsi.com.