Commentary: Spec raises bar for IP and SoC verification

Thomas L. Anderson
(03/18/2004 8:00 PM EST)

  Everyone knows that design reuse is essential for system-on-chip (SoC) development and that functional verification consumes the largest portion of the development process. Reuse of blocks from previous-generation chips or related chips within the same organization is universal, and acquisition of design IP from internal or external sources is quite common among SoC design teams.

Although reuse shortens the design time, verification takes 60-80% of the development effort for most SoC projects and functional verification is the dominant task. Most other verification tasks are highly automated; for example equivalence checking and most physical verification steps require relatively little user interaction. However, the process of developing verification models, writing tests, setting up for testbench automation, and debugging test results is enormously time-consuming.

Recognizing the growing challenges for chip functional verification, the Virtual Socket Interface Alliance (VSIA) has a Development Working Group (DWG) addressing this area. Since VSIA is primarily focused on Virtual Components (VCs), high-quality design IP that is suitable for reuse, the DWG provides a link between the worlds of design reuse and functional verification.

The Functional Verification DWG concentrates on best practices for the development of VCs, the deliverables (including documentation) that the VC providers should supply, and best practices for proper integration of the IP into the SoC. Establishing these criteria has required a broad range of expertise from VC providers, SoC developers and EDA vendors providing tools and libraries for reuse. Companies participating companies in the DWG have included Cadence, Elixent, Hewlett-Packard, IBM, Infineon, Intel, Mentor Graphics, Motorola, Palmchip, Synopsys and Verisity Design.

Virtual Socket Interface Alliance (VSIA) has a Development Working Group (DWG) addressing this area. Since VSIA is primarily focused on Virtual Components (VCs), high-quality design IP that is suitable for reuse, the DWG provides a link between the worlds of design reuse and functional verification.

The Functional Verification DWG concentrates on best practices for the development of VCs, the deliverables (including documentation) that the VC providers should supply, and best practices for proper integration of the IP into the SoC. Establishing these criteria has required a broad range of expertise from VC providers, SoC developers and EDA vendors providing tools and libraries for reuse. Companies participating companies in the DWG have included Cadence, Elixent, Hewlett-Packard, IBM, Infineon, Intel, Mentor Graphics, Motorola, Palmchip, Synopsys and Verisity Design.

The DWG recently released the ">The scope of the deliverables is quite broad, ranging from traditional elements such as testbenches and simulation test suites to assertions, formal verification constraints and other information needed for emerging verification techniques. Since not all VC providers and SoC developers use the same verification techniques, many deliverables are either optional or conditional depending upon specific VC or SoC attributes.