ASICFPGA releases new ISP core supporting AXI4-Lite, AXI4-Stream, new AE, and new AWB
March 10, 2023 -- ASICFPGA has announced the release of a new ISP core and demo board that supports AXI4-Lite, AXI4-Stream interface, new AE, and new AWB. The ISP cores, which include the HDR, Star, and Pro versions, support Multiple Pixel Processing of 1, 2, or 4 pixels per clock. Additionally, the new core is capable of supporting 4Kp60 and 4Kp120 at the FPGA device.
Features of new ISP core:
- Support for image sensors ranging from 256x256 to 8192x8192 in size, including 4Kp60 and 4Kp120
- Multiple pixel processing of 1, 2, or 4 pixels per clock
- Support for AXI4-Lite and AXI4-Stream interfaces
- Improved dynamic range with new AE of 17x15 windows and RGB Histograms
- Improved White balance with new AWB of 128x96 windows and Color temperature detection
- HDR processing for two/three multiple exposure images
- WDR (Shadow/Highlight compensation, back light compensation)
- Defect correction
- Lens shading correction
- High-quality interpolation
- New advanced 2D noise reduction and 3D Motion Adaptive noise reduction
- Color correction
- Gamma correction
- Edge enhancement
Feature of new demo board:
- Support Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit
- Support for 4K HDMI output
- Support for Sony IMX585 image sensor with a size of 1/1.2 inches and 2.9um x 2.9um pixel size
- Capable of 4K resolution and 3 frames DOL-HDR at 30fps
- Capable of 4K resolution and 2 frames Clear HDR at 30fps
- Capable of normal mode at 4K resolution and 30/60fps
Related Semiconductor IP
- UHD Image Signal Processing (ISP) Pipeline
- Low-Power ISP
- ISP, Image Signal Processing, Real-time Pixel Processor for Automotive
- Small-size ISP (Image Signal Processing) IP ideal for AI camera systems.
- Image Signal Processing (ISP) RTL IP for IR/Mono/RGB Bayer/RGB-IR/PDAF/HDR/Fish Eye/3A Sensors Image Process to Human/Machine Vision
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