ARM, MIPS aim to take the high ground at processor forum

ARM, MIPS aim to take the high ground at processor forum
By Peter Clarke, Semiconductor Business News
April 8, 2003 (11:20 a.m. EST)
URL: http://www.eetimes.com/story/OEG20030407S0062

LONDON — ARM Holdings Inc. is set to reveal details of the AMBA 3.0 version of its on-chip interconnect protocol and extensions to its most recent ARMv6 architecture.

Meanwhile rival company MIPS Technologies Inc. is preparing to discuss a complete high-performance 32-bit micro-architecture at this year's Embedded Processor Forum, June 16-19 at the Fairmont Hotel, San Jose, California, the company said

Thus, ARM and MIPS, the leading proponents of processor cores available for license, appear posed to battle for the high-performance high ground at the conference while rival companies such as SuperH Inc, a joint venture between STMicroelectronics NV and Renesas Technology Corp., and Tensilica are due to provide details of SIMD support (single-instruction multiple data) for their respective embedded processor offerings.

ARM recently recruited a Russian computer scientist for its assault on the embedded processing high ground (see April 7 story).

Infineon Technologies is set to deliver on a previously announced initiative (see November 4, 2002, story) to offer a dual threading architecture for embedded applications. Tuning the microprocessor-to-memory interface so that one virtual processor can act on data while the other is waiting is expected to reduce power consumption. Indeed, the Infineon presentation kicks off a low-power thread at the conference.

On the second day reconfigurability takes a prominent position in the morning session with Elixent Ltd. and Motorola SPS presenting papers on separate reconfigurable architectures.

Elixent's D-Fabrix, a checkerboard of ALUs, registers and memories, linked with FPGA-like programmable interconnect, has been discussed broadly. At the conference Alan Marshall, chief technology officer at Elixent, is due to present resul ts of the integration of D-Fabrix array with Toshiba's MeP, a 32-bit configurable multimedia RISC processor.

Toshiba opted to work with Elixent was announced in January (see January 27 story). Motorola first unwrapped its Reconfigurable Compute Fabric (RCF) technology at the company's Smart Networks Developers Conference, last month (see March 24 story) and will describe an RCF processor at the Embedded Processor Forum.

The final session on network processors includes presentations from Hifn, IBM, Ubicom and Wintegra.

Further details of the Embedded Processor Forum for 2003 can be found here.