Arm Updates CSS Designs for Hyperscalers' Custom Chips
By Sally Ward-Foxton, EETimes (February 21, 2024)
Arm recently upgraded its Arm Neoverse Compute Subsystem (CSS) designs with new CPU cores, aimed at companies building their own custom chips for the data center.
The market for custom chips in the data center is significant, according to Mohamed Awad, senior VP and general manager for Arm’s infrastructure line of business.
“[Hyperscalers] are redesigning systems from the ground up, starting with custom specs,” he said. “This works because they know their workloads better than anyone else, which means they can fine-tune every aspect of the system, including the networking acceleration, and even general-purpose compute, specifically, to optimize for efficiency, performance and ultimately TCO.”
Hyperscale data center operators have developed multiple generations of their own custom Arm-based CPU, including AWS Graviton, and Arm has been adopted for data center CPUs by companies, including Ampere and Nvidia.
To read the full article, click here
Related Semiconductor IP
- Multi-channel, multi-rate Ethernet aggregator - 10G to 400G AX (e.g., AI)
- Multi-channel, multi-rate Ethernet aggregator - 10G to 800G DX
- 200G/400G/800G Ethernet PCS/FEC
- 50G/100G MAC/PCS/FEC
- 25G/10G/SGMII/ 1000BASE-X PCS and MAC
Related News
- HCLTech and Arm collaborate on custom silicon chips optimized for AI workloads
- HCLTech and Arm Collaborate on Custom Silicon Chips Optimized for AI Workloads
- Synopsys Collaborates with Keysight Technologies to Deliver Integrated Custom Design Flow for 5G Designs
- SEMIFIVE collaborates with Arm to accelerate its custom SoC designs
Latest News
- How CXL 3.1 and PCIe 6.2 are Redefining Compute Efficiency
- Secure-IC at Computex 2025: Enabling Trust in AI, Chiplets, and Quantum-Ready Systems
- Automotive Industry Charts New Course with RISC-V
- Xiphera Partners with Siemens Cre8Ventures to Strengthen Automotive Security and Support EU Chips Act Sovereignty Goals
- NY CREATES and Fraunhofer Institute Announce Joint Development Agreement to Advance Memory Devices at the 300mm Wafer Scale