Apple M1 Processor, Passing on the Chiplets
By Don Scansen, EETimes (November 13, 2020)
Recent angry comments to EE Times‘ interview with Intel’s Ramune Nagisetty disparaged the current heterogenous integration and chiplet discussions as more of a rehash than an innovation and furthermore simply a way for American manufacturers to obfuscate their inability to stay at the leading edge of wafer fabrication. Although a great deal of the package-level integration that has been discussed is not ground-breaking innovation, there is little doubt that we are in the middle of a significant shift in integration away from system-on-chip (SoC) design.
Espousing the virtues of the SoC approach after that introduction is odd timing, but the latest foray into chip design at Apple was just announced. The M1, based around a custom piece of Apple SoC silicon, will power the new Macbook Air as well as some Macbook Pro and Mac Mini models. If we can take the promotional images provided by Apple at face value, calling the M1 processor die an SoC is certainly no understatement. Taking all due blame for my focus on the chiplet approach to integration, there is none of that here. Looking at the M1 die photo from Apple, breaking this type of design up into chiplets would not be an attractive prospect. The additional interconnection and communication overhead would create more headaches than it’s worth.
The other argument in favor of the SoC approach for Apple is that they are mostly past the point of using anyone else’s physical layout IP cores. They are responsible for the bulk of all the circuit blocks and focusing their efforts on keeping tight control over physical design and the hardware-software integration to optimize the system and (presumably) improve the user experience. They wouldn’t be buying either a vendor designed piece of silicon or hard IP core to be stitched into their processor design.
Before comparing the pure SoC design to current layouts that might be more amenable to a chiplet approach, there are a couple more things to mention about the M1.
To read the full article, click here
Related Semiconductor IP
- USB 20Gbps Device Controller
- Ultra-High-Speed Time-Interleaved 7-bit 64GSPS ADC on 3nm
- Fault Tolerant DDR2/DDR3/DDR4 Memory controller
- 25MHz to 4.0GHz Fractional-N RC PLL Synthesizer on TSMC 3nm N3P
- AGILEX 7 R-Tile Gen5 NVMe Host IP
Related News
- Probing the Apple M1's Hidden Depths
- Renesas Electronics Introduces R-Car M1 Series of Integrated SoCs Developed for Mid-Range Automotive Infotainment Systems
- Apple Begs the 64-Bit Question
- Apple Continues Familiar Design and Pricing Strategy with iPhone 5c, IHS Teardown Reveals
Latest News
- BrainChip Expands Global Reach, Announces Akida Boards and AI Development Kits Available at DigiKey
- Qualitas Semiconductor Successfully Demonstrates Live UCIe PHY IP at AI Infra Summit 2025
- Silicon Creations Announces 1000th Production FinFET Tapeout at TSMC and Immediate Availability of Full IP Library on TSMC N2 Technology
- Intel and NVIDIA to Jointly Develop AI Infrastructure and Personal Computing Products
- Comcores MACsec IP is compliant with the OPEN Alliance Standard