Altera® Expands Agilex™ FPGA Portfolio and Streamlines Developer Experience

Key News Highlights:

• As the largest pure-play FPGA solutions provider, Altera® is fueling growth by simplifying FPGA development and scaling programmable solutions to meet the needs of FPGA developers.
• Announces production availability of all Agilex™ FPGA and SoC FPGA device families.
• Launches new Visual Designer Studio tool in Quartus® Prime Software version 25.3 to bring a new level of ease-of-use to system design entry and integration.
• Increases logic density in Agilex 5 D-Series FPGAs and SoCs up to 2.5X to address edge AI, 4K/8K video, and 5G/6G wireless uses cases requiring higher capacity and greater memory throughput, along with new post-quantum cryptography (PQC) secure boot capability.

SAN JOSE, Calif. -- September 30, 2025 -- At its annual Innovators Day developer conference, Altera unveiled a wave of new FPGA hardware and software solutions that underscore the company’s ongoing investment in expanding the accessibility and scalability of programmable logic across a broad range of markets, including industrial, vision, defense, aerospace, communications, and data center. As the world’s largest pure-play FPGA solutions provider, Altera is uniquely positioned to deliver programmable solutions that are secure, scalable, and future-ready to meet the market demands created by today’s AI-fueled world.

“Altera is once again operating as a pure-play FPGA solutions provider, allowing us to operate with greater speed and agility so we can innovate faster, engage more closely with our customers, and respond rapidly to market shifts,” said Raghib Hussain, CEO of Altera. “Our investments in our channel and ecosystem partners, combined with the advancements we’ve made with our full-stack FPGA portfolio and tools, are helping to make FPGAs more accessible and lower the barriers to adoption. Altera is committed to enabling our customers to accelerate workloads in edge AI and embedded applications with architectures that deliver higher performance, lower latency, and improved power efficiency so they can differentiate faster and bring next-generation solutions to market with confidence.”

Altera announced production availability of all Agilex FPGAs device families, including Agilex 5 and Agilex 3 SoC FPGAs, which feature an integrated ARM processor subsystem. Altera’s power- and cost-optimized SoC FPGAs are designed to accelerate the deployment of FPGA-based edge AI use cases as well as traditional hardware-software co-processing applications by delivering the deterministic low-latency performance, system integration, and power efficiency that these systems require.

For applications requiring higher performance, capacity, and greater memory throughput, including edge AI inference, 4K/8K video, and 5G/6G wireless radio use cases, Altera is increasing the density of its mid-range Agilex 5 D-Series FPGAs and SoCs by up to 2.5X. The highest density Agilex 5 D-Series FPGAs now feature up to 1.6 million logic elements in a single device. The higher ratio of DSP blocks and logic density in D-Series devices, coupled with greater memory bandwidth, is built to address even more high-performance, space-constrained applications. In addition, Altera is increasing DDR5 interface speeds up to 5,600 MT/s and LPDDR5 up to 5,500 MT/s per interface instance for all Agilex 5 D-Series FPGAs, a 25 percent increase compared to prior specifications. The increased memory interface speeds offer significant benefits by boosting data throughput and improving overall system performance for a wide range of end applications.

All Agilex 5 D-Series devices incorporate post-quantum cryptography (PQC) secure boot capability on top of their best-in-class design security offering. Customers can start designing today using selected Agilex 5 D-Series devices in Quartus Prime Software.

Altera’s Quartus Prime Pro Edition version 25.3 continues to deliver industry-leading compile times and Fmax performance, reinforcing its position as a leading tool for FPGA design productivity.

As part of today’s news, Altera also released its Quartus Prime Software version 25.3, which delivers an enhanced developer experience through early access to new design tools that save FPGA design time and accelerate time-to-market.

The latest Quartus release includes early access to Visual Designer Studio, Altera’s 4^th-generation system integration tool. Visual Designer Studio accelerates IP integration by automating the process of connecting IP blocks in the design flow. The tool automatically suggests IP routing based on a user’s design requirements and applies valid IP connections to ensure proper functionality. Visual Designer Studio features a user-friendly drag-and-drop block view that allows users to visually place IP blocks and RTL code directly into the design and quickly trace data paths across the FPGA. Visual Designer Studio can slash the time it takes to get started on an FPGA design from 5 days to 2 hours when compared to RTL only.

The latest release achieves a 6 percent improvement in compile times compared to version 25.1.1, extending the overall compile time reduction to 27 percent since Agilex 7 FPGAs entered production (version 23.1). Designs also use an average of 6 percent fewer Adaptive Logic Modules (ALMs) while maintaining high Fmax performance (version 25.1.1). Powered by ongoing compiler and architecture optimizations, Quartus software enables designers to fit more logic into FPGAs and more easily meet performance targets, even after devices are in production. While results may vary by design, many users can expect faster compiles, reduced resource usage, and fewer timing closure iterations, accelerating time to market for complex FPGA projects.

Altera Quartus Prime Software version 25.3 is available for download now, along with the latest release of Altera’s FPGA AI Suite version 25.3, which accelerates the integration of AI models into an FPGA.

Extensive FPGA Ecosystem Accelerates Time-to-Market

Altera’s robust partner ecosystem plays a pivotal role in enhancing the FPGA developer experience and helping to streamline the FPGA development process. Altera has over 300 registered partners within the Altera Solution Acceleration Partner (ASAP) Program. Through ASAP, developers gain access to Altera-approved partners who offer IP, software, hardware, and design services that reduce design complexity and help to accelerate time-to-market by up to 50 percent. For more information about the ASAP program, visit https://www.altera.com/asap.

About Altera

Altera is a leading supplier of programmable hardware, software, and development tools that empower designers of electronic systems to innovate, differentiate, and succeed in their markets. With a broad portfolio of industry-leading FPGAs, SoCs, and design solutions, Altera enables customers to achieve faster time-to-market and unmatched performance in applications spanning industrial automation, audio/video, robotics, aerospace, defense, data centers, telecommunications, edge AI, and more. For more information, visit www.altera.com.