Adiabatic's first silicon cuts power 50 percent

Adiabatic's first silicon cuts power 50 percent
By Peter Clarke, EE Times
October 13, 2003 (1:40 p.m. EST)
URL: http://www.eetimes.com/story/OEG20031013S0028

Cambridge, England - Adiabatic Logic Ltd., a startup developing power-saving circuitry and intellectual property, has tested first silicon of its Intelligent Output Driver and reports that IOD technology achieved power saving of more than 50 percent compared with traditional I/O schemes.

The IOD technology is a form of lossless signaling that has the potential to save up to a theoretical maximum of 75 percent of the power wasted in resistor-terminated line-driving schemes, the company said.

"Achieving over 50 percent power savings with our first test chip is a significant achievement, and we will improve this through a program of incremental development, which will include a further tapeout with refinements before the yearend," said Geoff Harvey, chief technology officer of Adiabatic Logic, here, in a statement.

Designed to replace the conventional pad drivers on an IC, the IOD cell uses a patented energy-recycling technique, whi ch in simulated tests delivered 50 to 75 percent power saving in chip I/O.

The patented technology includes a self-tuning, two-step, three-pole switching scheme that recycles much of the power used during interchip communications and does not require changes at the receiver I/O pad. Harvey demo'd the principle using discrete circuitry prior to the formation of Adiabatic Logic, which was spun out of the Cambridge Technology Group (see www.eetimes.com/story/OEG20030512S0035).

At the monolithic level, IOD uses the speed of submicron CMOS to actively mimic the voltage-current drive characteristics of a classic driver with a source (or series) terminator resistor. It does so in such a way that the bulk of the current is delivered to the load capacitance nonresistively from a reservoir capacitance maintained at a midrail voltage, assisted by the inherent inductance of the load. The on-chip reservoir capacitance delivers charge on rising edges and recovers charge on falling edges, thereby recycling energy that is conventionally wasted.

Adiabatic went to Austriamicrosystems AG (Unterpremstatten, Austria) for the first silicon proof of IOD, using a 0.6-micron process technology.

"It was the quickest and most convenient way to test the circuit, and we didn't want the first test complicated by deep-submicron design rule issues," said Harvey. He added that the test chip comprises a couple of IOD pads and some conventional CMOS I/O pads for comparison. As well as saving power consumption by recycling energy, the IOD pad drivers were able to operate at higher frequencies. "IOD outpaced the conventional pad driver," he said.

Simon Payne, Adiabatic Logic's CEO, said the company was already preparing to improve on the 50 percent power-saving figure as it refines the recycling circuit and moves to finer geometry. Payne said that 0.35-micron CMOS was a likely next node, adding that "it's quite possible we'll go to 0.18 micron as well."

Payne declined to discuss which other foundries or chip makers Adiabatic might work with. Austriamicrosystems currently only manufactures down to 0.35-micron CMOS, so to go finer would require additional manufacturing partners.

Payne said these decisions are likely to be made along with partnership and licensing discussions. He confirmed that Adiabatic is in discussions with both foundries and integrated device manufacturers.

"We have had a lot of interest in IOD in recent months from right across the electronics industry, a clear indication of just how important conserving power has become, particularly for those developing portable battery-powered electronic devices," Payne said. "However, now that we have working test chips that prove out the technology at IC level, we hope to be having more serious discussions with potential partners about licensing our IOD technology."