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Search (63)
Compare 63 IP from 20 vendors (1 - 10)
  • Verification IP for UCIe
    • Avery UCIe VIP provides a comprehensive verification solution featuring an advanced UVM environment that incorporates constrained random traffic gener ation, robust D2D and LogPHY layer controls and error injection, protocol checks and coverage, functional coverage, protocol analyzer-like features for debug ging, and performance analysis metrics.
    • PCIe/CXL VIP supports FDI/RDI adapters for complete stack verification. With the advanced capabilities of Avery VIP, engineers can work more efficiently, develop more complex tests, and work on more complex topologies, such as bifurcation.
    Block Diagram -- Verification IP for UCIe
  • UCIe Chiplet PHY & Controller
    • Compliant with the UCIe specification (2.0 & 1.1)
    • Flexible Structure, easy to customize (Pre-hardened PHY tuned to Customer Spec, PHY + Adapter Layer, PHY + Adapter Layer + Customized Protocol Layer)
    • Supports the CXS/AXI using the streaming package (AXI Interface bandwidth up to 89%)
    Block Diagram -- UCIe Chiplet PHY & Controller
  • Universal Chiplet Interconnect Express(UCIe) VIP
    • The UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of your UCIe designs
    • The UCIe VIP is fully compliant with UCIe Specification version 1.0 and supports all the layers of the UCIe stack, such as FDI, RDI, LogPHY, PCIe, and CXL protocols
    • The UCIe VIP is also very user-friendly and flexible, with simple APIs, easy integrations, and configurable parameters
    Block Diagram -- Universal Chiplet Interconnect Express(UCIe) VIP
  • The UCIe CONTROLLER IP
    • The UCIe IP solution includes D2D Adapter layer which supports streaming/PCIe/CXL/Raw flitformats, supports both standard and advanced mainband links and sideband links
    Block Diagram -- The UCIe CONTROLLER IP
  • UCIe D2D Adapter
    • The D2D Adapter for UCIe is a scalable adapter layer between one or more protocol components and the UCIe PHY, which ensures efficient data transfer across the UCIe Link by seamlessly coordinating with the Protocol Layer and Physical Layer.
    • By minimizing logic on the main data path, it delivers a low-latency, optimized pathway for protocol Flits.
    Block Diagram -- UCIe D2D Adapter
  • Simulation VIP for UCIE
    • Protocol Layer Features
    • Streaming mode
    • PCIe mode
    • Protocol FDI LSMs
    Block Diagram -- Simulation VIP for UCIE
  • UCIe Verification IP
    • Available in native SystemVerilog (UVM/OVM /VMM) and Verilog.
    • Unique development methodology to ensure highest levels of quality.
    • Availability of various Regression Test Suites.
    • 24X5 customer support.
    Block Diagram -- UCIe Verification IP
  • UCIe 2.0 Verification IP
    • Available in native SystemVerilog (UVM/OVM /VMM) and Verilog.
    • Unique development methodology to ensure highest levels of quality.
    • Availability of various Regression Test Suites.
    • 24X5 customer support.
    Block Diagram -- UCIe 2.0 Verification IP
  • D2D UCIe 1.1
    • Compatible with UCIe v1.1 specification
    • Features single-ended, source-synchronous, and DDR I/O signaling
    • Supports 32-bit (16-bits TX + 16-bit RX) data bus per module for standard packages
    • Offers a high clock frequency up to 16GHz
    Block Diagram -- D2D UCIe 1.1
  • UCIe Die-to-Die Chiplet Controller
    • High configurability and customizability
    • Defines packets to communicate with a link partner using different AXI parameters
    • Supports raw streaming modes
    • Provides various Flit formats in UCIe v1.1 (filt format 2: 68B flit format, flit format 3/4: standard 256B flit format, and flit format 5/6: latency optimized 256B flit format)
    Block Diagram -- UCIe Die-to-Die Chiplet Controller
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