pci express IP
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531
IP
from 34 vendors
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10)
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PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
- Supports 2.5Gb/s serial data rate
- Utilizes 8-bit or 16-bit parallel interface to transmit and receive PCI Express data
- Full Support for Auxiliary Power (Vaux) for Energy aware systems like Multi-Port Host Controllers
- Data and clock recovery from serial stream on the PCI Express bus
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PCI Express - Configurable PCI Express 4.0 IP
- Compliant with "PCI Express™ Base Specification, Rev. 4.0 Version 1.0"
- Compliant with "PHY Interface For the PCI Express, SATA, and USB3.1 Architectures"
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PCI Express 4.0 PHY
- Compiles with PCIe 4.0, 3.1, 2.1, 1.1 and PIPE 4.4.1 Specifications
- Supports all power saving modes (P0, P0s, P1, P2) as defined in PIPE 4.4.1 spec.
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PCI Express Gen 1/2/3/4 Phy
- TSMC advanced 16 nm FFC CMOS process
- Available in 1X, 4X, 8X, and 16X configuration
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PCI Express Gen 1/2/3/4 Phy
- 2.5/5.0/8/16 Gbps per lane interface optimized for PCI Express applications
- Compliance to PCI Express 1.0a, 1.1 and 2.1, 3.1 and 4.0 PIPE specifications
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PCI Express x1, x4 Root Complex Lite IP Core
- Download demo bitstream from the PCI Express Demo page.
- Visit the PCI Express Solutions page for other demos, boards and development kits.
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PCI Express to VME64x Transparent Bridge
- Complete PCI Express to VME64x Master/Slave Bridge
- Improved performance compared to currently available ASIC solutions
- PCI Express x4 GEN1/2
- VME64x supported modes: SLT, BLT, MBLT, 2eVME and 2eSST
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PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- Complies with the PCI Express® Base 3.0 Specification, rev.3.1
- Supports Endpoint, Root-Port, Dual-Role, Switch configurations
- Supports x16, x8, x4, x2, x1 at Gen3, Gen2, Gen1 speeds
- Implements one Virtual Channel
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PCI Express Endpoint Core
- 250 MHz Reference Clock Input
- 125 MHz, 16-bit Data Path User Interface
- Creates TLPs without ECRC or Sequence Number during Transmit
- Receives Valid TLPs without Sequence Number during Receive
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Lancero Scatter-Gather DMA Engine for PCI Express
- PCIe I/O performance: 200 MB/s x1 Gen 1 up to 3360 MB/s x8 Gen 2
- Easily connect logic and high-speed I/O peripherals to PCI Express
- Target Bridge supports Avalon Memory Mapped custom logic
- SGDMA Engine supports Avalon Streaming burst access devices
