Image processing IP

The Intel FPGA Video and Image Processing Suite is a collection of Intel FPGA intellectual property (IP) functions that you can use to facilitate the development of custom video and image processing designs
These Intel FPGA IP functions are suitable for use in a wide variety of image processing and display applications, such as studio broadcast, video conferencing, AV networking, medical imaging, smart city/retail, and consumer.

32bit DVP interface, 24bit ISP pipeline
Dual pixel per cycle throughput
Wide Dynamic Range Tone Mapping (WDR)
Multi-exposure HDR (Native/build in HDR, Compand output, DOL/Stagger, Stagger output)

The ACAP HDR Image Signal Processing Framework is intended to showcase a complete logicBRICKS IP suite implementation of High-Dynamic Range (HDR) Image Signal Processing (ISP) pipeline in an embedded design based on AMD-Xilinx ACAP programmable devices.
The HDR ISP pipeline enables crisp camera video under altering and rough lighting conditions in next generation multi-channel embedded systems for use in automotive, surveillance, medical, aerospace and similar video and vision AI applications.

Supports DVP Input Interface
Input color formats: 8-bit, 10-bit, 12-bit Bayer; 8-bit, 10-bit YUV BT.601, BT.656; 8-bit, 10-bit monochrome
SW Register Configuration: 32-bit AHB Slave
Frame rate control, configurable output FPS range from 60fps to 1fps

image processing IP