The logiREF-ACAP-MULTICAM-ISP ACAP HDR Image Signal Processing Framework enables Xylon logiVID-ACAP-ISP HDR ISP Evaluation Kit for Versal ACAP users to quickly utilize the provided hardware platform for the development of AMD-Xilinx Versal Adaptive Compute Acceleration Platform (ACAP) based embedded multi-camera vision systems. The HDR ISP pipeline enables crisp camera video under altering and rough lighting conditions in next generation multi-channel embedded systems for use in automotive, surveillance, medical, aerospace and similar video and vision AI applications.
The logicBRICKS logiISP-UHD IP core enables parallel processing of multiple Ultra HD video inputs in different AMD-Xilinx devices, ranging from the small AMD-Xilinx Artix FPGAs to the latest AMD-Xilinx Versal Adaptive Compute Acceleration Platform (ACAP) devices. The design showcases how to connect high-quality inputs from automotive-grade cameras to on-board post-processing solutions or feed the stream to hardware-accelerated integrated neural networks running on this adaptive computing acceleration platform.
All logicBRICKS IP cores are supplied with bare-metal and appropriate Linux software drivers. The provided video capture and display demo applications run in Linux OS.
ACAP HDR Image Signal Processing Framework
Overview
Key Features
- Complete HDR ISP video processing framework for multi-channel vision and AI systems
- Demonstrates logicBRICKS HDR ISP pipeline for parallel processing of three UHD automotive video cameras
- Fully compatible with Xylon logiIVID-ACAP-ISP HDR ISP Evaluation Kit for Versal ACAP based on AMD-Xilinx ACAP Versal VCK190 Evaluation Kit
- Runs on Linux OS, includes logicBRICKS software drivers and demo applications made with AMD-Xilinx Vitis™ Unified Software Platform 2021.2
- Demonstrates programmable logic savings achieved by multiplexing of ISP functions
- Includes licensed* Xylon logicBRICKS IP cores
- Resolutions: 3840x1920 Input and 3840x2160 Output
- HDMI display output
- Jump-starts development and saves valuable design time
Block Diagram
Applications
- AD/ADAS,
- AI,
- guided robotics,
- drones,
- machine vision,
- AR/VR
- other vision applications
Technical Specifications
Related IPs
- UHD Image Signal Processing (ISP) Pipeline
- 5M pixel sensor support Image Signal Processing (ISP) IP
- HDR Image Signal Processor
- FXAFE030HH0L is an Analog Front End IP for image processing applications. FXAFE030HH0L is fabricated in UMC 40 nm logic LP/HVT Low-K process to implement a signal processing solution for scanners, video and imaging applications. _x005F_x000D_
- Digital Signal Processor (DSP) for image processing
- 8-13M pixel sensor support High Quality Image Signal Processing (ISP) IP