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eDP IP

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Search (35)
Compare 35 IP from 13 vendors (1 - 10)
  • eDP 1.5a RX PHY Samsung 14nm
    • Compliant to DisplayPort v1.4, eDP v1.4, and eDP v1.5a
    • Supports data rates from Reduced Bit Rate (RBR:1.62 Gbps) to High Bit Rate 3 (HBR3: 8.1Gbps), and user configurable custom B/Ws
    • Supports for eDP v1.4b features, such as PSR1 and PSR2
    Block Diagram -- eDP 1.5a RX PHY Samsung 14nm
  • eDP Transmitter IP
    • Supports eDP 1.4b specification
    • Supports full eDP Transmitter functionality
    • Supports multi lanes upto 4 lanes.
    • Supports main link, Aux link and Hot plug functionality.
  • eDP Receiver IP
    • Supports eDP 1.4b specification
    • Supports full eDP Receiver functionality
    • Supports multi lanes upto 4 lanes.
    • Supports main link, Aux link and Hot plug functionality.
  • eDP 1.4 Receiver
    • Compliant with Embedded DisplayPort 1.4 specification
    • Support for up to 4 Dual-Speed lanes at 1.62 Gbit/s and 2.7 Gbit/s
    • Supports Enhanced Framing Mode
    • Integrated High-bandwidth Digital Content Protection (HDCP) version 1.4
    Block Diagram -- eDP 1.4 Receiver
  • eDP 1.4 Transmitter
    • Compliant with Embedded DisplayPort 1.4 specification
    • Main Link supports 1, 2 or 4 lanes at 1.62Gbps, 2.7Gbps and 5.4Gbps
    • 4 channel S/PDIF Digital Audio Input
    • Supports Enhanced Framing Mode
    Block Diagram -- eDP 1.4 Transmitter
  • 250Mbps to 8.1Gbps Multi-protocol SerDes PMA, wire-bond
    • Layout for wirebond packaging
    • Very wide CDR range -- operates with data rates from 0.25Gbps to 8.1Gbps
    Block Diagram -- 250Mbps to 8.1Gbps Multi-protocol SerDes PMA, wire-bond
  • 125Mbps to 16Gbps Multi-protocol SerDes PMA
    • Very wide CDR range -- operates with data rates from 0.25Gbps to 12.7Gbps
    • Extremely low jitter suitable for Enterprise SerDes applications
    Block Diagram -- 125Mbps to 16Gbps Multi-protocol SerDes PMA
  • eDP1.4/DP1.3 TX Link IP
    • eDP version 1.4a, DP version 1.3 compliant receiver
    • Supports HDCP Decryption
    • Supports both 1.62/8.1Gbps data rate
    Block Diagram -- eDP1.4/DP1.3 TX Link IP
  • DisplayPort Receiver Link Controller
    • Silicon proven on multiple ASIC and FPGA processes
    • Capable of operating without a host CPU in low complexity applications
    • Horizontal and vertical video delimiter signals with 1, 2 or 4 pixels per output cycle, supporting up to 16K resolution output; deep color and HDR support
    • 1.62 to 8.1 Gbps link rate across 1, 2, or 4 lanes
    Block Diagram -- DisplayPort Receiver Link Controller
  • DisplayPort Transmitter Link Controller
    • Silicon proven on multiple ASIC and FPGA processes with multiple PHY partners.
    • 1, 2 or 4 pixels per input cycle, supporting up to 16K resolution input per source
    • 1.62-8.1Gbps link rate across 1,2, or 4 lanes
    • SST or MST operation
    Block Diagram -- DisplayPort Transmitter Link Controller
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Semiconductor IP