eDP1.4/DP1.3 TX Link IP
Overview
eDP (Embedded Displayport) Transceiver Link/PCS IP core is compliant with eDP 1.4a/DP 1.3 specification.
Key Features
- eDP version 1.4a, DP version 1.3 compliant receiver
- Supports HDCP Decryption
- Supports both 1.62/8.1Gbps data rate
- Supports 1, 2 and 4-lanes main link
- Supports both Default and Enhanced Framing Mode
- Supports SST mode
- Supports only video packet
- Supports 18/24/36-bit RGB digital video output format
- I2C master interface for DDC/CI connection
- Various test modes (Link Quality Measurement, etc)
- Interface to external HDCP key storage
- Configuration registers programmable via SPI interface
Block Diagram
Technical Specifications
Maturity
silicon-proven
Related IPs
- Link Layer Controller
- Link Protocol Engine
- APB Fundamental Peripheral IP, Serial Interface controller for multiple frame formats, SSP (by TI), SPI (by Motorola), Microwire (by NS), I2S (by Philips), AC - link (by Intel) and SPDIF (by Intel), Soft IP
- Synchronous Data Link Controller
- PCI Express PHY serial link PIPE Transceiver IP cell/hard macro
- Complete memory system supporting any combinations of SDR SDRAM, DDR, DDR2, Mobile SDR, FCRAM, Flash, EEPROM, SRAM and NAND Flash, all in one IP core