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Compare 41 IP from 15 vendors (1 - 10)
  • ARINC 664 (AFDX) End System DO-254 IP Core
    • The ARINC 664 (AFDX) End System DO-254 IP Core (AFDX ES IP) implements an AFDX End System as specified in ARINC 664 Part 7 “Avionics Full-Duplex Switched Ethernet (AFDX) Network”.
    • The AFDX ES IP supports MII, RMII, GMII or SGMII as PHY interfaces. Therefore, it is able to transmit and receive at 10 Mbps, 100 Mbps or 1000 Mbps, making full usage of the bandwidth.
    Block Diagram -- ARINC 664 (AFDX) End System DO-254 IP Core
  • ARINC 708A Verification IP
    • Available in Verilog, System Verilog, and UVM.
    • Control Word information can be user-configurable / Random. (Protected By parity).
    • Data word header will be according to the 270 271 label Frame received from Control Word.
    • Support for Hazards, Faults, and Errors.
    Block Diagram -- ARINC 708A Verification IP
  • ARINC 818 Verification IP
    • Full ARINC 818 source device and sink device functionality.
    • Supports ARINC specification 818 - 2.
    • Supports serial & parallel bit ordering.
    • Supports following bit rates
    Block Diagram -- ARINC 818 Verification IP
  • ARINC 825 Verification IP
    • Supports ARINC specification 825 - 2.
    • Supports one of the following data rates
    • 83.33 Kbit/s
    • 125 Kbit/s
    Block Diagram -- ARINC 825 Verification IP
  • ARINC 664 Verification IP
    • Supports IEEE 802.3 10/100 Mbit/s Full duplex Ethernet links
    • Supports all word structures and protocol necessary to establish bus communication as per the specs.
    • Supports simplex,twisted shielded pair data bus standard Mark.
    • Supports LRU with multiple transmitters and receivers communicating on different buses.
    Block Diagram -- ARINC 664 Verification IP
  • ARINC 429 Verification IP
    • Supports ARINC SPECIFICATION 429 PART 1-17.
    • Supports all word structures and protocol necessary to establish bus communication as per the specs.
    • Supports simplex, twisted shielded pair data bus standard Mark 33 Digital Information Transfer System bus.
    • Supports LRU with multiple transmitters and receivers communicating on different buses.
    Block Diagram -- ARINC 429 Verification IP
  • ARINC 419 Verification IP
    • Supports ARINC REPORT 419 - 3.
    • Supports 32 bit words containing a 24 bit data portion containing the actual information, and an 8 bit label describing the data itself.
    • Supports Transmission rates at 11 ± 3.5 kbps.
    • Supports Bipolar Return-to-Zero encoding format.
    Block Diagram -- ARINC 419 Verification IP
  • ARINC 825 Synthesizable Transactor
    • Supports ARINC REPORT 825 - 2
    • Supports transmission data rates from 83.333 Kbps to 1Mbps
    • Supports one-to-many communication and also peer-to-peer communication
    • Supports all the four frame types
    Block Diagram -- ARINC 825 Synthesizable Transactor
  • ARINC 429 Synthesizable Transactor
    • Supports ARINC SPECIFICATION 429 PART 1-17
    • Supports all word structures and protocol necessary to establish bus communication as per the specs
    • Supports simplex, twisted shielded pair data bus standard Mark 33 Digital Information Transfer System bus
    • Supports LRU with multiple transmitters and receivers communicating on different buses
    Block Diagram -- ARINC 429 Synthesizable Transactor
  • ARINC 419 Synthesizable Transactor
    • Supports ARINC REPORT 419 - 3
    • Supports 32 bit words containing a 24 bit data portion containing the actual information, and an 8 bit label describing the data itself
    • Supports transmission rates at 11 ± 3.5 kbps
    • Supports bipolar Return-to-Zero encoding format
    Block Diagram -- ARINC 419 Synthesizable Transactor
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