ARINC 664 Verification IP

Overview

The ARINC 664 Verification IP is compliant with ARINC SPECIFICATION 664 PART 7 and verifies MAC-to-PHY and PHY-to-MAC layer interfaces of designs with a Ethernet interface. It can work with SystemVerilog, Vera, SystemC, E and Verilog HDL environment.The SmartDV's ARINC 664 Verification IP is fully compliant with ARINC SPECIFICATION 664 PART 7 and provides the following features

ARINC 664 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

ARINC 664 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Supports IEEE 802.3 10/100 Mbit/s Full duplex Ethernet links
Supports all word structures and protocol necessary to establish bus communication as per the specs.
Supports simplex,twisted shielded pair data bus standard Mark.
Supports LRU with multiple transmitters and receivers communicating on different buses.
Supports Traffic shaping in accordance with Bandwidth Allocation Gap (BAG)
Supports the following Upper layer protocols:
- IPV4
- UDP
Supports Transmit Redundancy Controller.
Glitch insertion and detection
Supports all types of errors insertion/detection as given below:
- LDU Sequence Number Error
- Parity Errors
- Word Count Errors
- CRC Errors
- Time Out Errors
Notifies the test bench of significant events such as transactions, warnings and protocol violations.
Status counters for various events.
Monitor supports detection of all protocol violations
Callbacks in Transmitter and Receiver for various events
Built in functional coverage analysis.
FIFO depth programmable.
ARINC 664 Verification IP comes with complete testsuite to verify each and every feature of ARINC 664 Part 7 specification.

Benefits

Faster testbench development and more complete verification of ARINC 664 designs.
Easy to use command interface simplifies testbench control and configuration of ARINC 664 TX and RX.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the testcases.
Examples showing how to connect various components, and usage of TX,RX BFM and Monitor.
Detailed documentation of all class, task and function's used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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