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WUSB IP

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Compare 767 IP from 61 vendors (1 - 10)
  • USB 2.0 HS PHY Interface
    • The USB PHY IP is UTMI interface compatible and a dedicated circuit for full-function USB 2.0 transceivers.
    • It is a mixed-signal circuit, with the analog part including the transmitting and receiving circuits, level conversion circuits, bus driver circuits, etc., and the digital part including the transmitting and receiving and speed switching control circuits, encoding and decoding circuits, serial-to-parallel and parallel-to-serial conversion circuits, as well as digital CDR circuits, etc.
  • USB 1.1 Device Controller
    • The USB device core is compliant with revision 1.1. of the USB Specification.
    • The core consists of a fixed piece of logic consisting of a serial interface engine and control endpoint.
    • To this fixed logic various endpoints can be easily added.
    Block Diagram -- USB 1.1 Device Controller
  • USB Full Speed Transceiver
    • Exceeds USB 2.0 Full Speed specification.
    • Trimmed pull up resistor.
    • Enable / suspend feature.
    • DPF and UFP options available.
    Block Diagram -- USB Full Speed Transceiver
  • USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
    • Supports 40 Gbps, 20 Gbps, 10 Gbps, and 5 Gbps data rates
    • Supports 480 Mbps, 12 Mbps, and 1.5 Mbps data rates
    • x1 and x2 configurations (USB 3.2 and USB 3.1 PHY only)
    • Low active and standby power
    • Small area for low silicon cost
    Block Diagram -- USB 4.0 V2 PHY - 4TX/2RX, TSMC N3P , North/South Poly Orientation
  • USB 2.0 PHY
    • Compliant with USB2.0 and USB1.1 specification
    • Compliant with UTMI Specification Version 1.0
    • Supports HS(480Mbps)/FS(12Mbps) /LS(1.5Mbps) modes
    • USB Data Recovery and Clock Recovery on receiving
    • SYNC and EOP generation on transmit packets and detection on receive packets
  • USB 1.1 PHY, Support Low Speed and Full Speed - HLMC 55nm
    • USB 1.1 PHY, Support Low Speed and Full Speed;
  • USB 1.1 PHY, Support Low Speed and Full Speed - HHGrace 110nm
    • USB 1.1 PHY, Support Low Speed and Full Speed;
  • Verification IP for USB
    • Avery VIP for USB is a comprehensive solution for verification of USB-based designs ranging from the USB 2.0, 3.x, and 4.0 standards, including xHCI host controllers and USB mass storage class standards for UAS and BOT.
    • USB VIP allows users to verify their designs by developing custom tests at several levels of abstraction.
    Block Diagram -- Verification IP for USB
  • USB 2.0 Mass Storage Devices Design Platform
    • The USB 2.0 Mass Storage Design Platform is a complete, integrated solution, dedicated to a wide range of USB-based Mass Storage Devices.
    • You can use it in various applications, like portable flash memory, digital audio player, card reader or digital camera.
  • USB 2.0 Human Interface Devices Design Platform
    • The USB 2.0 HID Design Platform is a complete, integrated solution, dedicated to a wide range of USB-based Human Interface Devices, like mouse, keyboard, and tablet.
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