VPU IP
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13
IP
from 7 vendors
(1
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10)
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VPU R3.0 on Artix 7 100T
- Video processing system suitable for high-speed, high resolution video systems
- HDMI Full-HD (1920x1080p) input & output at 60fps
- High-speed processing at 60fps
- Uses FPGA for parallel processing
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VPU R2.6 on Artix 7 200T
- Video processing system suitable for high-speed, high resolution video systems
- HDMI Full-HD (1920x1080p) input & output at 60fps
- High-speed processing at 60fps
- Uses FPGA for parallel processing
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VPU R3.0 on Artix 7 200T
- Video processing system suitable for high-speed, high resolution video systems
- HDMI Full-HD (1920x1080p) input & output at 60fps
- High-speed processing at 60fps
- Uses FPGA for parallel processing
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VPU R1.0 on Artix 7 200T
- Video processing system suitable for high-speed, high resolution video systems
- HDMI Full-HD (1920x1080p) input & output at 60fps
- High-speed processing at 60fps
- Uses FPGA for parallel processing
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NPU IP family for generative and classic AI with highest power efficiency, scalable and future proof
- Support wide range of activations & weights data types, from 32-bit Floating Point down to 2-bit Binary Neural Networks (BNN)
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Vector Unit
- 64-bit
- FP & Int, 8b to 64b
- DLEN up to 2048b
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64-bit RISC-V Multicore Processor with 1024-bit Vector Extension
- 64-bit in-order dual-issue 8-stage CPU core with up to 1024-bit Vector Processing Unit (VPU)
- Symmetric multiprocessing up to 8 cores
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64-bit CPU with RISC-V Vector Extension
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- RISC-V vector extension
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64-bit CPU with RISC-V Vector Extension
- AndeStar™ V5 Instruction Set Architecture (ISA), compliant to RISC-V technology
- RISC-V vector extension
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Image Signal Processing Pipeline IP core
- ISPido is a fully RTL Image Signal Processing Pipeline
- Configurable via AXI4-LITE protocol (e.g. with RISCV)
- Complete and configurable ISP Pipeline includes:
- Defective Correction pixel
