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VESA FEC IP

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Compare 16 IP from 6 vendors (1 - 10)
  • VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
    • VESA DisplayPort 1.4 compliant
    • Reed-Solomon RS (254,250) FEC, 10-bit symbols
    • Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
    • DisplayPort main 8b/10b encoder included (Tx only)
    • Status and control can be done with signals or optionally via an integrated APB register module (Rx)
    Block Diagram -- VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
  • FEC RS (254,250) IIP
    • VESA Display Port version 1.4/2.0/2.1 compliant.
    • Supports full FEC functionality.
    • Supports Reed Solomon (254,250) FEC, 10-bit symbols.
    • Supports the input and output data widths of multiples of 10-bit.
    Block Diagram -- FEC RS (254,250) IIP
  • FEC RS (198,194) IIP
    • Supports the Universal Serial Bus 4 Specification and VESA Display Port version 2.0/2.1 Specification.
    • Supports full FEC functionality.
    • Supports Reed Solomon (198,194) FEC, 8-bit symbols.
    • Supports the input and output data widths of multiples of 8-bit.
    Block Diagram -- FEC RS (198,194) IIP
  • DisplayPort 1.4 FEC Transmitter (Tx) ASIL-B
    • VESA DisplayPort 1.4 compliant
    • Reed-Solomon RS (254,250) FEC, 10-bit symbols
    • Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
    • DisplayPort main 8b/10b encoder included (Tx only)
    Block Diagram -- DisplayPort 1.4 FEC Transmitter (Tx) ASIL-B
  • DisplayPort 1.4 FEC Receiver (Rx)
    • VESA DisplayPort 1.4 compliant
    • Reed-Solomon RS (254,250) FEC, 10-bit symbols
    • Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
    • DisplayPort main 8b/10b encoder included (Tx only)
    • Status and control can be done with signals or optionally via an integrated APB register module (Rx)
    Block Diagram -- DisplayPort 1.4 FEC Receiver (Rx)
  • DisplayPort 1.4a IP Core
    • 1,2,3 & 4 lanes
    • 1.62, 2.7, 5.4 and 8.1 Gbps link rate (includes eDP rates)
    • HDCP 1.3 / 2.2
    • MST support, up to 4 streams
  • Simulation VIP for DisplayPort
    • Device Support
    • Source, Sink, Link Training-Tunable PHY Repeater (LTTPR/retimer)
    • Main Link Interface
    • Serial, Parallel (10-bit, 20-bit, 40-bit)
    Block Diagram -- Simulation VIP for DisplayPort
  • HDMI 1.4/2.0/2.1 Verification IP
    • Protocol Checker fully compliant with HDMI Specification 1.4b, 2.0b and 2.1 compliant.
    • Full HDMI source and sink device functionality
    • Supports Video data coding.
    • Supports TERC4 coding and Control period codings.
    Block Diagram -- HDMI 1.4/2.0/2.1 Verification IP
  • Display Port 2.0 Verification IP
    • Full Display port 2.0 source device and sink device functionality.
    • Supports backward compatibility with previous versions upto DPv1.4a
    • Supports multi lanes upto 4 lanes.
    • Supports control symbols for framing.
    Block Diagram -- Display Port 2.0 Verification IP
  • Display Port Verification IP
    • Full Display port source device and sink device functionality.
    • Display port supports version 1.0,1.1,1.2,1.2a,1.3,1.4,1.4a and 2.0 specification.
    • Supports multi lanes upto 4 lanes.
    • Supports control symbols for framing(Both Default & Enhanced framing mode).
    Block Diagram -- Display Port Verification IP
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