DisplayPort 1.4 FEC Receiver (Rx)

Overview

The DisplayPort Forward Error Correction (FEC) Receiver IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 1.4 specification. Forward Error Correction is required to ensure glitch-free Display Stream Compression (DSC) bitstream transport.

Solution for High-Performance External Displays, UHD TV, USB-C/DisplayPort Accessories

Key Features

VESA DisplayPort 1.4 compliant
Reed-Solomon RS (254,250) FEC, 10-bit symbols
Two-way interleaving for 1-, 2- and 4-lane modes (4-lane mode requires 2 FEC IP core instances)
DisplayPort main 8b/10b encoder included (Tx only)
Status and control can be done with signals or optionally via an integrated APB register module (Rx)
Single unified APB interface supports 4-lane mode (Rx)
Performance monitoring and statistics counters (Rx)

Block Diagram

Applications

UHD monitors
DisplayPort 1.4 products
USB Type-C products
UHD TVs

Deliverables

Verilog RTL
Complete documentation
Expert technical support
Maintenance updates

Technical Specifications

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