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USB PHY IP

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Compare 628 IP from 38 vendors (1 - 10)
  • USB3.2 PHY
    • Reference Clock:
    • Internal PLL:
    • Data Transmit:
    • Data Receive:
  • USB 2.0 DRD Controller
    • Compliant with xHCI specification 1.2 defined for USB host controllers
    • Compliant with Universal Serial Bus (USB) Specification Revision 2.0.
    • Compliant with AMBA? AHB Protocol Specification.
    • Compliant with AMBA? AXI Protocol Specification.
  • USB2.0 PHY & Controller
    • Compliant with USB Specification Revision 2.0, 1.1
    • Configurable 8-bit or 16-bit UTMI interface compliant with UTMI+ Specification Level 3 Revision 1.0
    • Supports 480Mbps (HS), 12Mbps (FS) and 1.5Mbps (LS) serial data transmission
    • Supports low latency hub mode with 40-bit time round trip delay
  • USB2.0 OTG PHY
    • Compliant with USB Specification Revision 2.0, 1.1
    • Configurable 8-bit or 16-bit UTMI interface compliant with UTMI+ Specification Level 3 Revision 1.0
    • Compliant with OTG Supplement to the USB Specification Revision 2.0
    • Supports 480Mbps (HS), 12Mbps (FS) and 1.5Mbps (LS) serial data transmission
  • USB 3.0 DRD Controller
    • Compliant with xHCI specification 1.2 defined for USB host controllers
    • Compliant with Universal Serial Bus (USB) Specification Revision 2.0.
    • Compliant with Universal Serial Bus (USB) Specification Revision 3.0
    • Compliant with AMBA? AHB Protocol Specification.
  • USB3.1/3.0 PHY & Controller
    • Reference Clock:
    • Internal PLL:
    • Data Transmit:
    • Data Receive:
  • Type-C PHY
    • Area: 1.92mm2 (1600um x 1200um) including IO and ESD
    • Note: The area parameters are for reference only. Please refer to the final LEF file for the actual value.
    • Compliant with DP1.2 and USB3.0 specifications
    • Support DP 2/4-lane configuration
  • eUSB2 PHY
    • Fully compliant with Embedded Universal Serial Bus 2.0 (eUSB) electrical specification.
    • Designed for advanced process nodes (7nm and below)
  • HSIC PHY
    • Consumes <90mW during data transfer
    • Consumes <50uW when not transferring data
    • Uses standard chip digital and IO supplies
    • Low pin count
  • USB 2.0 PHY - TSMC 55ULPeF25 x1, OTG
    • Ported to over 50 different processes and configurations ranging from 65-nm to 14/16-nm FinFET
    • Supports the USB 2.0 protocol and data rate (480 Mbps)
    • Supports the USB Type-C specification
    • USB femtoPHY, USB nanoPHY and USB picoPHY offer a tunability feature that allows quick, post-silicon adjustments that occur due to process variations, or unexpected chip and board parasitic, without modifying the existing design
    Block Diagram -- USB 2.0 PHY - TSMC 55ULPeF25 x1, OTG
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