USB 3.1 PHY

Overview

Proven PHY IP for USB3.1 with supporting multi-protocol feature

The ^® IP for 10Gbps Multi-Protocol PHY simplifies the design process without compromising performance, power, or silicon die area. Crafted for mobile, wireless IoT, consumer, and automotive designs, the IP is designed for multi-protocols running on a single PHY macro and is compliant with USB 3.1, PCI Express^® (PCIe^®) 3.1, DisplayPort TX v1.4, Embedded DisplayPort TX v1.4b, SATA 3, 10G-KR and QSGMII/SGMII.

Key Features

Supports USB 3.1, PCIe 3.1, DP-TX v1.4/eDP-TX v1.4b, SATA 3, 10G-KR and QSGMII/SGMII
Multi-protocol support for simultaneous independent links
Supports SRIS and internal SSC generation
Supports PCIe L1 sub-states
Automatic calibration of on-chip termination resistors
Supports internal and external clock sources with clock active detection
SCAN, BIST, and serial/parallel loopback functions

Benefits

Multi-Protocol with Multi-Link Capability: Single PHY macro offers optimum SoC configurability with the protocol mix and match
Optimized Performance, Power, and Area: Best fit for applications requiring performance with small footprint
Comprehensive Test Feature Enable Rapid SoC Development: Extensive BIST and DFT enable ease of integration, faster bring-up, and quick debugging

Block Diagram

Deliverables

Verilog behavioral modules for PHY module
Verilog testbench with configuration files and sample tests
Liberty timing model
Layout abstract in LEF format
GDSII with flat netlist for LVS

Technical Specifications

Samsung

Silicon Proven: 7nm

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