USB 2.0 High Speed PHY IP

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Compare 59 IP from 13 vendors (1 - 10)
  • Low/Full Speed USB Physical Layer
    • USB PHY Interface
    • USB1.1/2.0 Compliant
    • Low and Full speed support
    • UTMI Interface to USB Controller
    Block Diagram -- Low/Full Speed USB Physical Layer
  • USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core
    • Support SW controlled host/device role switching.
    • Support Fullspeed and Lowspeed
    • Support Control, Bulk, Interrupt and Isochronous Transfer Types
    • Support L1/L2 power saving modes for USB 2.0 port
    Block Diagram -- USB 2.0 OTG High / Full / Low- Speed Dual Role IP Core
  • USB 2.0 High Speed PC Host Controller (USB-IF Certified)
    • USB-IF Certified full-feature PC Host Controller solution
    • Next generation USB controller architecture producing the smallest size, lowest power, and maximum configurability
    • Compliant with USB 2.0 specification revision 1.0 with latest ECNs
    • Compliant with xHCI specification revision 1.1
  • USB 2.0 High Speed Dual-Role Device Controller (USB-IF Certified)
    • USB-IF Certified full-feature PC Host solution
    • Next generation USB controller architecture producing the smallest size, lowest power, and maximum configurability
    • Compliant with USB 2.0 specification revision 1.0 with latest ECNs
    • Compliant with xHCI specification revision 1.1
  • USB 2.0 High Speed Device Controller (USB-IF Certified)
    • USB-IF Certified full-feature PC Host solution
    • Next generation USB controller architecture producing the smallest size, lowest power, and maximum configurability
    • Compliant with USB 2.0 specification revision 1.0 with latest ECNs
    • Compliant with xHCI specification revision 1.1
  • USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm
    • Complies with USB specifications Rev. 2.0 and 1.1
    • Complies with UTMI+ specification Level 3, Rev. 1.0
    • Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
    • Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes
    Block Diagram -- USB 2.0 PHY GlobalFoundaries 12nm, 22nm, 28nm, 40nm
  • USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
    • Complies with USB specifications Rev. 2.0 and 1.1
    • Complies with UTMI+ specification Level 3, Rev. 1.0
    • Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
    • Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes
    Block Diagram -- USB 2.0 PHY TSMC 5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm, 65nm, 130nm, 180nm
  • USB 2.0 PHY IP, Silicon Proven in TSMC 22ULP
    • Compliant with USB2.0 and USB1.1 specification
    • Compliant with UTMI Specification Version level 3.
    • Supports HS(480Mbps)/FS(12Mbps) /LS(1.5Mbps) modes
    • All required terminations, including 1.5Kohm pullup on DP and DM, and 15Kohm pull-down on DP and DM are internal to chip
    Block Diagram -- USB 2.0 PHY IP, Silicon Proven in TSMC 22ULP
  • USB 2.0 PHY
    • Complies with USB specifications, rev. 2.0 and 1.1
    • Complies with UTMI+ specification, level 3, rev. 1.0
    • Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
    • Supports 8-bit unidirectional Parallel Interface Engine (PIE) bus for HS, FS and LS modes, and Serial Interface Engine (SIE) for FS and LS modes
    Block Diagram -- USB 2.0 PHY
  • USB 2.0 PHY For On-The-Go Controller
    • Complies with USB specifications, rev. 2.0 and 1.1
    • Complies with UTMI+ specification, level 3, rev. 1.0
    • Supports OTG USB 2.0
    • Supports 480Mb/s (HS), 12Mb/s (FS) and 1.5MB/s (LS) serial data transmission rates
    Block Diagram -- USB 2.0 PHY For On-The-Go Controller
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