IP Catalog > UHS-II

UHS-II IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (17)
Compare 17 IP from 7 vendors (1 - 10)
  • UHS-II Device Controller
    • Compliance with Part 1 UHS-II Addendum Version 1.02
    • Compliance with Part A2 SD Host controller specification version 4.10 & Part1 Physical layer specification version 4.20
    • Programmable 1 or 2 Data lane Configuration
    • Supports all type of packets
    Block Diagram -- UHS-II Device Controller
  • SD4.0 / UHS-II Host Controller & PHY
    • + Support Standard Capacity (SDSC), High Capacity (SDHC) and Extended Capacity (SDXC) cards
    • + 1 and 4-bit parallel legacy SD interface, and serial UHS-II interface
    • + All bus interface modes: legacy SD (DS, HS, SDR12, SDR25, SDR50, SDR104, DDR50) and UHS-II (FD156, HD312)
    • + Data transfer rate up to 104 Mbps with 4 parallel SD data lines
  • SD 4.1 UHS-II PHY for TSMC 12nm FF
    • Compliant to SD Specifications Part 1 UHS-II Specification Volume 2: PHY* and SD Specifications Part 1 UHS II Specification Volume 1: System and Protocol”
  • UHS-II PHY for SD4/SD5 TSMC 12nm FF
    • Compliant with SD Specifications Part 1 UHS-II Addendum v1
    • Supports data rate between 390 Mbps to 1.56 Gbps per lane
  • UHS-II PHY for SD4/SD5 TSMC 16nm FF
    • Compliant with SD Specifications Part 1 UHS-II Addendum v1
    • Supports data rate between 390 Mbps to 1.56 Gbps per lane
  • SD 4.0 UHS-II PHY in TSMC 40LP
    • Compliant to SD Specifications Part 1 UHS-II Specification Volume 2: PHY* and SD Specifications Part 1 UHS II
    • Specification Volume 1: System and Protocol”
    • Per lane data rate between 390Mb/s to 1.56Gb/s
    • Supports peak interface speed of 3.12Gb/s (Half-duplex); 1.56Gb/s in Full-duplex mode
    Block Diagram -- SD 4.0 UHS-II PHY in TSMC 40LP
  • SD 4.0 UHS-II PHY TSMC 28nm HPM North-South
    • Compliant with SD Specifications Part 1 UHS-II Addendum v1
    • Supports data rate between 390 Mbps to 1.56 Gbps per lane
    • Supports peak interface speed of 3.12 Gbps in Half-duplex mode; 1.56 Gbps in Full-duplex mode
    • Sub-LVDS differential PHY signaling
    Block Diagram -- SD 4.0 UHS-II PHY TSMC 28nm HPM North-South
  • SD Card Controller - Verifies SD card interface functionality, ensuring reliable data transfer and compliance with specifications
    • The SD Card Controller Verification IP (VIP) is a tool designed to ensure the proper functionality and performance of SD card memory interfaces in SoCs. It validates key operations like read/write cycles, error handling, and power management across multiple SD card versions.
    • This VIP is widely applicable in various fields, from SoC design validation to mobile devices and embedded systems. It guarantees reliable data transfer and smooth integration with SD card interfaces in industries such as automotive, consumer electronics, IoT, and more
    Block Diagram -- SD Card Controller - Verifies SD card interface functionality, ensuring reliable data transfer and compliance with specifications
  • Simulation VIP for SD CARD and SDIO
    • SD Card device standard
    • Speed Range A and B
    • Default Speed Range A and faster Range B support
    • PHY-LINK I/F
  • SDIO UHS II Verification IP
    • Supports SD specification UHS-II Adddendum version 2.00 compliant.
    • Supports Part E1 SDIO specification version 4.10.
    • Supports SD specification physical layer version 4.0/4.20/5.0/5.10/6.0/6.10/7.0/7.10/8.0(Draft).
    • Supports bi-directional receiver/transmitter (2ch) supporting both Full Duplex and Half Duplex modes.
    Block Diagram -- SDIO UHS II Verification IP
×
Semiconductor IP