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Simulation VIP for SD CARD and SDIO

Overview

In production since 2012 for many production designs.

SD CARD Cadence Verification IP (VIP) upgrades the SD CARD and SDIO verification platform with Ultra High Speed Type II (UHS-II) support. It allows seamless verification of legacy SD CARD and SDIO protocol (version 3.00 and below) and the latest UHS-II interface. The UHS-II interface allows access to traditional SD CARD and SDIO applications through the SD-TRAN layer and to the UHS-II memory space through the CM-TRAN layer. The VIP allows full-stack UHS-II interface verification (TRAN + LINK + PHY) through the serial interface and protocol IP verification (stripped of PHY) through the PHY-LINK I/F defined in the specification.

SD Host Controller Cadence Verification IP (VIP) is based on Part E1 SDIO (SD input/output) specification defined for SD and SPI bus interface specification for SDIO including register specification. It is defined for SDIO Card, Embedded SDIO device, and Combo Card.

Supported specifications:

For SD CAR – Part 1 Physical Layer Specification Version 4.00 and Part 1 UHS-II Addendum Version 1.00

For SD Host Controller – SD Specifications Part E1 SDIO Simplified Specification Version 3.00 and Part 1 Physical Layer Specification Version 3.01.

Key Features

  • SD Card device standard
  • Speed Range A and B
    • Default Speed Range A and faster Range B support
  • PHY-LINK I/F
    • Interface defined in Appendix-F allows verification of protocol IP independently
  • Half-duplex
    • Half-duplex (2L-HD) mode of operation that doubles data throughput
  • Data Bust Streaming
    • Allows multiple model instances to be connected using ring connection
  • Data Burst Retry
    • Data Burst Retry support through the simulation of recoverable error
  • Embedded Flash
    • Support of an embedded flash as defined in eSD specification
  • Area
    • Support of the boot area, user area, and other partition through CMD43 and
  • Fast Boot
    • Support of fast boot feature
  • Boot Code Loading
    • Boot code can be loaded from one of the model instances designated as boot device
  • Low Power Mode
    • Low Power Mode supported through configuration register setting
  • SD Host Controller standard
  • Multiple Modes
    • Supports both SD mode and SPI mode
  • Multi-function
    • Supports IO only, Memory only, and IO+Memory
  • UHS-I
    • Supports UHS-I initialization and transmission
  • Bus width
    • 1-bit mode and 4-bit mode (SD Mode only)
  • Initialization
    • IO Aware and Non-IO Aware initialization sequences for both SD and SPI modes
    • Supports auto initialization and manual initialization
  • Multi Block Read/Write
    • For both IO and memory commands. Busy signaling supported with write commands for SD and SPI
  • Clock Stop and Voltage Switching
    • Clock stop and voltage switching command support
  • Read Wait and Suspend Resume
    • Read wait and suspend and resume functionality
  • Abort
    • Data transfer abort for both IO and memory
  • Dynamic Reset
    • Dynamic reset commands
  • CARD Interface Register Access
    • Commands to access card interface fixed registers

    Technical Specifications

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