Single port SRAM IP
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TSMC CLN5FF High Density Single Port SRAM Compiler
- The High Density Single Port SRAM operates within voltage range from 0.675 V to 0.825 V and junction temperature range from -40 °C to 125 °C. The available supported macro size is configurable from 512 bits to 576K bits. The Compiler is divided into 1 groups according to their column selection numbers (Mux=8).
- ? Pins and metal layers
- – 1P3M (1X_h_1Xb_v): 3 metal layers used and top metal is MXb.
- – Power mesh supported with M3 pins
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Single Port SRAM compiler - Memory optimized for ultra high density and high speed - compiler range up to 64 k
- Smart periphery design to reach the highest density
- Memory designed with SVT MOS for periphery and SVT HD PRBC from TSMC for memory core
- Flexible architecture
- To offer several performance trade-offs for any memory size
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This fifo uses external onchip single port memory to store data.
- 1. Configurable Depth.
- 2. Configurable Width.
- 3. Configurable Clock freq.
- 4. Uses External OnChip Single Port Memory for Storage of Data
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Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- Memory generator
- SVT TSMC Bit-cell for memory core and SVT MOS for memory periphery
- Migration of a mass produced architecture already available in other geometries(90nm, 55 nm)
- Up to 30% denser than competition SRAM
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Single Port SRAM compiler - Memory optimized for high density and low power - compiler range up to 320 k
- ConfigurationSVT/HVT MOS for memory peripheryuHD HVT pushed rule bit-cell from foundry Designed with 4 metal layers, routing enabled over the memory in metal 4 within free routing tracksMigration on an existing architecture already available for other processes (90, 85, 55 nm)Smart periphery design to reach the highest densityUp to 20% denser than standard memory generators at 55 nmUltra low leakage designData retention mode at nominal voltage (1.2 V) and low voltage (0.7 V): for 4x leakage reductionLow dynamic powerPartitioned arrayVariable write-mask capability Easy integrationMUX optionsData range flexibility allows easy addition of bits for redundancy or ECC purposesAddress range flexibility allows easy addition of single rows for redundancy purposes The Dolphin qualityComplete mismatch validation of the memory architecture taking in account local and global dispersionOptional BIST for industrial fabrication test of instances
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Global Foundries 55nm Low Power LowK Process synchronous high density low power single port SRAM memory compiler.
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Global Foundries 55nm Low Power LowK Process synchronous high density low power single port SRAM memory compiler.
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Global Foundries 55nm LowPower LowK Process synchronous high density low power single port SRAM memory compiler.
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UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler.
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UMC 80nm Embedded High Voltage process standard synchronous high density single port SRAM memory compiler with redundancy.