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SLVS-EC IP

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Search (14)
Compare 14 IP from 3 vendors (1 - 10)
  • SLVS-EC Verification IP
    • Full SLVS-EC transmitter device and receiver device functionality.
    • SLVS-EC supports version 2.0 specification.
    • Supports the following system topologies between CIS and DSP
    • Basic Topology
    Block Diagram -- SLVS-EC Verification IP
  • SLVS-EC TRANSMITTER IIP
    • Compliant with SLVS-EC specification 2.0.
    • Full SLVS-EC transmit functionality.
    • Supports the following system topologies between CIS and DSP
    • Basic Topology
    Block Diagram -- SLVS-EC TRANSMITTER IIP
  • SLVS-EC RECEIVER IIP
    • Compliant with SLVS-EC specification 2.0.
    • Full SLVS-EC receive functionality.
    • Compatible with following system topologies between CIS and DSP
    • Basic Topology
    Block Diagram -- SLVS-EC RECEIVER IIP
  • SLVS-EC Interface for FPGA
    • Compliant with SLVS-EC Specification Version 1.2
    • Support various functions defined by the SLVS-EC Link layer
    Block Diagram -- SLVS-EC Interface for FPGA
  • SLVS-EC TX PHY - 10GBPS 8-Lane - TSMC 12FFC
    • SLVS-EC ver.3.0 compliant
    • Data Rate: Up to 10Gbps / lane
    • Number of data lane: 8
    • Support input clock: 24MHz, 54MHz, 37.125MHz, 72MHz, 74.25MHz
    Block Diagram -- SLVS-EC TX PHY - 10GBPS 8-Lane - TSMC 12FFC
  • FEC RS (255,251) IIP
    • HDMI specification 2.1/2.1a and Scalabale Low Voltage Signaling with Embedded Clock (SLVS_EC) compliant.
    • Supports full FEC functionality.
    • Supports Reed Solomon (255,251) FEC, 8-bit symbols.
    • Supports the input and output data widths of multiples of 8-bit.
    Block Diagram -- FEC RS (255,251) IIP
  • Multi-PHY Receiver Link Controller
    • CD12842M8LRM3BM4AIP312P5 is a link IP that allows you to link a camera module or CMOS image sensor (CIS) to a host system.
    • This LINK IP is a soft macro IP that has the function of converting MIPI CSI2 protocol or other interface protocol to the data for application layer.
  • Camera Combo Receiver - 5.0Gbps 8-Lane - TSMC 12FFC, 7FF
    • The CL12842M8RM3AM5AIP5000 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processor) and DSP.
    • The CL12842M8RM3AM5AIP5000 is designed to support data rate in excess of maximum 5Gbps utilizing SLVS-EC ver.2.0 / MIPI D-PHY ver.1.2 / HiSPi / sub-LVDS / CMOS 1.8V interface specification.
  • Camera Combo Receiver - 2.5Gbps 8-Lane - TSMC 28nm HPC
    • The CL12832M8R2JM3QIP2500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to ISP (Imaging Signal Processer) and DSP.
    • The CL12832M8R2JM3QIP2500 is designed to support data rate in excess of maximum 2.5Gbps utilizing SLVS-EC / MIPI D-PHY v-1.2/ CMOS 1.8V interface specification.
  • Camera Combo Receiver - 2.4Gbps 8-Lane - TSMC 28nm HPC
    • The CL12832M8R2JM3KIP2400 is designed to support data rate in excess of maximum 2.4Gbps utilizing SLVS-EC / sub-LVDS / CMOS 1.8V interface specification.
    • The CL12832M8R2JM3KIP2400 can change Interface type to same PAD for changing mode.
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