Multi-PHY Receiver Link Controller
Overview
CD12842M8LRM3BM4AIP312P5 is a link IP that allows you to link a camera module or CMOS image sensor (CIS) to a host system. This LINK IP is a soft macro IP that has the function of converting MIPI CSI2 protocol or other interface protocol to the data for application layer. A great way to implement a camera serial interface (MIPI CSI2) with Curious PHY IP.
Key Features
- SLVS-EC v1.2 / MIPI CSI2 v1-2 / MIPI D-PHY v1-2 Compliant
- Supports Curious Multi-PHY
- Supports PHY mode:
- SLVS-EC, MIPI DPHY/CSI2 Link Layer, Sub-LVDS Interface, CMOS Input
- Maximum Lane Number: DATA 8Lane CLOCK 2Lane
- Supports Link Ports: 2 Port
- SLVS-EC :
- *Data Format: RAW8/10/12/14/16
- *Supports HDR(DOL)
- *Supports CRC32
- MIPI DPHY/CSI2 Link Layer:
- *Data Format: RAW8/10/12/14/16, YUV422/420, RGB 888/555/565/101010
- *Supports HDR(DOL DINFO) and HDR(Virtual Channel)
- *Supports DESKEW function.
- *Various application interface are supported by custom option.
- Sub-LVDS Interface:
- *Data Format: RAW8/10/12/14/16
- *Supports SOF/SOL/EOL/EOF/Pixel Data transfer mode
- *Supports Sony SAV/EAV code transfer mode
- *Supports HDR(DOL DINFO) and HDR(DOL HINFO)
- CMOS:
- *Direct data output pins from PHY Analog Layer
- Register control:
- *Supports AMBA-APB I/F or Direct pin inputs
- TEST I/F:
- *Supports PHY Analog layer loop back test mode
- *Supports Monitor test outputs for PHY internal signals
Benefits
- We are IP design professional engineering company, so we can provide the high quality and good performance solution. Also we can provide not only single-interface PHY but also multi-interface PHY. And we can provide the Link layer IP which connect to Curious multi-interface PHY.
- Our business is very flexibility IP license model, and then we have a lot of license to many sensor companies.
- Our products can contribute to your business.
Applications
- Camera Application
- Security Camera
- Mobile-Phone Camera
- DSC(Digital Still Camera)
- Medical Camera
- SLR
- 3D Camera
- Camcorder
- ISP(Image Signal Processer)
Deliverables
- Verilog-HDL encrypted RTL
- Document
- Specification
- Curious PHY-LINK connection
- Timing Information
- DFT Information
- CSI2 register calculation sheet
- Test Bench / Sample TEST vector for basic function check
- PHY function model (included in Curious PHY IP)
Technical Specifications
Maturity
Available
Availability
Now