Next generation CMOS image sensor interface
SLVS-EC is the next-generation, high-speed interface for high-resolution CMOS image sensors.
This standard is tolerant of lane-to-lane skew because of embedded clock technology that simplifies board-level design of high-speed and long-distance data transmission.
Originally developed and licensed by Sony, SLVS-EC is now starting to be supported by multiple image sensor suppliers.
Specifications
| Feature | Description |
|---|---|
| Number of Lanes | 1, 2, 4, 6, 8 |
| Baud Grade |
1 (1.152 to 1.25 Gbps) 2 (2.304 to 2.5 Gbps) 3 (4.608 to 5.0 Gbps - supported in v2.0) |
| Bit per Pixel | 8, 10, 12, 14, 16 |
| CRC | Limited* |
| ECC | Supported |
| Embedded Data | Supported |
| Dynamic Mode Change | Supported |
| Multiple Stream | If needed |
Supported Devices
- Intel Cyclone V GX/SX (v1.2)
- Intel Cyclone 10 GX (v1.2 / 2.0)
- Intel Arria 10 GX/SX (v1.2 / 2.0)
- Xilinx Artix 7 (v1.2)
- Xilinx Kintex 7 (v1.2 / 2.0)
- Xilinx Kintex Ultrascale (v1.2 /2.0)
- Xilinx Kintex Ultrascale (v1.2 / 2.0)
evice Resource Utilization
Resource Utilization in case of 8 LANE Full Configuration
| Items | Cyclone® V GX | Arria® 10 GX | ||
| w/o ECC | w/ECC | w/o ECC | w/ECC | |
| ALMs | 4711 | 8242 | 3930 | 7555 |
| Total Registers | 4328 | 6664 | 3778 | 6079 |
| Total block memory bits | 4096 | 13312 | 2560 | 11776 |
