SATA PHY IP
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300
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10)
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SATA PHY
- Serial ATA II Revision 2.6 compliant
- Gen1i, Gen1m, Gen2i, Gen2m compliant
- Gen1x, Gen2x compatible
- Initialization and power saving modes
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SATA 6G PHY in GF (40nm, 28nm)
- Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
- AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
- AMBA 4 AXI and ACE-Lite bus interfaces
- Memory data protection and memory address parity protection
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SATA 6G PHY
- ? 6-Gbps transmission rate through standard SATA cable
- ? Spread-spectrum clock (SSC) generation and absorption
- ? Programmable down-spread (+4,980 ppm through -4,980 ppm)
- ? Fully clock-forwarded transceiver interface, configurable using soft PMA layer above hard macro PHY
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SATA 3 PHY
- Serial ATA III Revision 3.3 compliant
- Gen1i, Gen1m, Gen2i, Gen2m compliant
- Gen1x, Gen2x compatible
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SATA 6G PHY in UMC (40nm, 28nm, 22nm)
- Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
- AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
- AMBA 4 AXI and ACE-Lite bus interfaces
- Memory data protection and memory address parity protection
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SATA 6G PHY in TSMC (40nm, 28nm, 16nm, 12nm, N7)
- Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
- AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
- AMBA 4 AXI and ACE-Lite bus interfaces
- Memory data protection and memory address parity protection
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SATA 6G PHY in SMIC (40nm, 28nm)
- Compliant with SATA/eSATA v3.3, AHCI v1.3 and SATA PIPE v4.3 specifications
- AMBA 2.0 AHB and AMBA 3 AXI subsystem interfaces
- AMBA 4 AXI and ACE-Lite bus interfaces
- Memory data protection and memory address parity protection