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RLDRAM 3 IP

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  • RLDRAM Controller MACO Core
    • Controller operates at half the memory clock frequency
    • Allows programmable burst lengths of
    • Includes a reconfigurable refresh counter
    • Command & Write Data pipeline to maximize throughput
    Block Diagram -- RLDRAM Controller MACO Core
  • Universal Multi-port Memory Controller for RLDRAM2/3, DDR4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2
    • The UMMC Controller is a highly flexible and configurable design. It is targeted for high bandwidth access and low power consumption such as next generation mobile, DDR/LPDDR networking and consumer applications.
    • The controller architecture is carefully tailored to achieve reliable high-frequency operation with dynamic power management and rapid system debug capabilities.
    Block Diagram -- Universal Multi-port Memory Controller for RLDRAM2/3, DDR4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2
  • Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2
    •  
    • The UMMC (Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2) is a highly flexible and configurable design that supports RLDRAM2, RLDRAM3 and JEDEC compliant DDR5, DDR4 3DS, DDR4, DDR3, LPDDR3, LPDDR3 and LPDDR2 memories.
    • It is targeted for high bandwidth access and low power consumption such as next-generation mobile, networking and consumer applications. The controller architecture is carefully tailored to achieve reliable high-frequency operation with dynamic power management and rapid system debug capabilities
    Block Diagram -- Universal Multi-port Memory Controller for RLDRAM2/3, DDR5/4/3, DDR4 3DS and LPDDR3/2 and LPDDR3/2
  • Memory Interface
    • Memory Interface generates through a Graphic User Interface the unencrypted Verilog or VHDL design files, UCF constraints, and simulation script files to simplify the memory interface design process.
    • Memory modules (DIMM) are supported for DDR3, DDR2 and DDR SDRAMs.
    • OS Support
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