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Power Management Network IP

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Compare 248 IP from 34 vendors (1 - 10)
  • Power efficient, high-performance neural network hardware IP for automotive embedded solutions
    • Power efficient, high-performance
    • For automotive embedded solutions
  • Data Movement Engine - Turnkey network compute subsystem for data movement applications.
    • Industrial Networking: Rapid packet processing of data through multiple, switched ethernet ports with support for factory automation protocols
    • 5G/6G Communications: Scalable L2/L3 Ethernet switch with flexible port counts/speeds, including TSN and security
    • Automotive Gateway: High-speed data packet networking with multiple communication interfaces and support for switching and bridging
    • Datacenter Infrastructure: Standalone data processing units to handle highly multiplexed data streams corresponding to millions of network connections with high efficiency and low power
  • Run-time Reconfigurable Neural Network IP
    • Customizable IP Implementation: Achieve desired performance (TOPS), size, and power for target implementation and process technology
    • Optimized for Generative AI: Supports popular Generative AI models including LLMs and LVMs
    • Efficient AI Compute: Achieves very high AI compute utilization, resulting in exceptional energy efficiency
    • Real-Time Data Streaming: Optimized for low-latency operations with batch=1
    Block Diagram -- Run-time Reconfigurable Neural Network IP
  • Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network
    • "Ethernet/TSN/ARINC664P7 EndSystem with customizable number of ports up to 1 Gbps.
    • Support IEEE 1588 PTPV2 as GrandMaster or User
    • Safe & Secure Ethernet communication
    • Multi-protocol
    Block Diagram -- Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network
  • Multi Protocol IO Concentrator (RDC) IP Core for Safe and Secure Ethernet Network
    • Ethernet/ARINC664P7 Switch with customizable number of ports up to 1 Gbps.
    • Support IEEE 1588 PTPV2 as GrandMaster or User
    • Safe & Secure Ethernet communication
    • Multi-protocol : CAN, ARINC429, MIL-STD-1553, TSN
    Block Diagram -- Multi Protocol IO Concentrator (RDC) IP Core for Safe and Secure Ethernet Network
  • Low power, high speed, and high density configurable Double Density SRAM
    • Based on patent-pending 1T cell design
    • Implemented with unmodified standard CMOS logic process
    • Best-in-class active power, leakage current, density, and speed
    • Supports large instances (e.g. 32Mbit)
  • DC/DC Buck Regulator
    • High efficiency buck regulator (up to 95% in peak), thanks to dual mode (dm) controller
    • Pulse Frequency Modulation (PFM) mode at low load and Pulse With Modulation (PWM) mode at high load.
    • Low Bill-Of-Material: fully integrated feedback and active compensation loop do not require additional external passive components.
    • Behavioral models: ease integration in SoC and optimized Power Management Network (PMNet) by verifying mode transitions as well as noise propagation
  • Linear regulator, low-noise optimized for sensitive analog loads such as CODEC and Reference
    • Starring a PSRR of -65 dB at 20 kHz and a low intrinsic noise, combined with a low quiescent current of 110 uA, the nLR-VAIPO helps optimize the power management network for audio handheld applications such as smartphone and tablet.
    • Small footprint: only 0.12 mm2 (including bandgap reference and POK circuit)
    • Minimization of the overall system power, through the support of 3 modes of operation: normal, shutdown and bypass
    • Eases integration in SoC nLR-VAIPO is delivered with behavioral models. These new views enable to build an optimized Power Management Network (PMNet) by verifying mode transitions as well as noise propagation.
    Block Diagram -- Linear regulator, low-noise optimized for sensitive analog loads such as CODEC and Reference
  • Linear regulator, low-noise optimized for sensitive analog loads such as CODEC and Reference
    • Starring a PSRR of -65 dB at 20 kHz and a low intrinsic noise, combined with a low quiescent current of 110 uA, the nLR-VAIPO helps optimize the power management network for audio handheld applications such as smartphone and tablet.
    • Small footprint: only 0.12 mm2 (including bandgap reference and POK circuit)
    • Minimization of the overall system power, through the support of 3 modes of operation: normal, shutdown and bypass
    • Eases integration in SoC nLR-VAIPO is delivered with behavioral models. These new views enable to build an optimized Power Management Network (PMNet) by verifying mode transitions as well as noise propagation.
    Block Diagram -- Linear regulator, low-noise optimized for sensitive analog loads such as CODEC and Reference
  • DC/DC Buck Regulator
    • High efficiency buck regulator (up to 95% in peak), thanks to dual mode (dm) controller
    • Pulse Frequency Modulation (PFM) mode at low load and Pulse With Modulation (PWM) mode at high load.
    • Low Bill-Of-Material: fully integrated feedback and active compensation loop do not require additional external passive components.
    • Behavioral models: ease integration in SoC and optimized Power Management Network (PMNet) by verifying mode transitions as well as noise propagation
    Block Diagram -- DC/DC Buck Regulator
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