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PCIe Gen 2 IP

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Search (33)
Compare 33 IP from 14 vendors (1 - 10)
  • PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 28HKMG
    • Compatible with PCIe base Specification
    • Full compatible with PIPE4.2 interface specification
    • Independent channel power down control
    • Implemented Receiver equalization Adaptive-CTLE to compensate insertion loss
    Block Diagram -- PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 28HKMG
  • PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 40LL
    • Compatible with PCIe base Specification
    • Full compatible with PIPE4.2 interface specification
    • Independent channel power down control
    • Implemented Receiver equalization Adaptive-CTLE to compensate insertion loss
    Block Diagram -- PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 40LL
  • Low-jitter Ring PLL
    • 10MHz up to 640MHz input frequency range (65G)
    • 14MHz up to 2.8GHz output frequency range (65G)
    • Small footprint (0.02mm^2 in 65G
    • Integrated Long Term Jitter typically 1ps RMS -- meets requirements for PCIe gen 1, 2, 3 and SATA 1, 2, 3 reference clock
  • PCIe Gen2 PHY
    • PCI Express Gen 2 and Gen 1 compliant
    • Supports various PCI Express modes and extensions
    • Programmable amplitude and pre-emphasis
    • Programmable receiver equalization
    Block Diagram -- PCIe Gen2 PHY
  • PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 55LL/SP/EF
    • Compatible with PCIe base Specification
    • Full compatible with PIPE4.2 interface specification
    • Independent channel power down control
    • Implemented Receiver equalization Adaptive-CTLE to compensate insertion loss
    Block Diagram -- PCIe 2.0 Serdes PHY IP, Silicon Proven in SMIC 55LL/SP/EF
  • PCIe Gen2 PHY
    • ? 5-Gbps data transmission rate
    • ? PIPE3-compliant transceiver interface, configurable using soft Physical Coding Sublayer (PCS)
    • layer above hard macro PHY
    • ? Supports 8-bit interface at 500-MHz operation
  • PCIe Multifunction IP Core for Intel FPGAs
    • Utilizes the Intel PCIe HIP block with up to 8
    • physical PCIe functions.
    • • Designs provides up to 8 AXI masters which
    • can be freely mapped to the PCIe functions
    Block Diagram -- PCIe Multifunction IP Core for Intel FPGAs
  • PCIe Multifunction IP Core for Xilinx 7 FPGAs
    • Extends the Xilinx integrated PCI-Sig compliant PCIe Hardblock by up to 6 true physical PCI Express Functions
    Block Diagram -- PCIe Multifunction IP Core for Xilinx 7 FPGAs
  • PCIe Gen1 PHY
    • ? 2.5-Gbps data transmission rate
    • ? Supports 16-bit interface at 250-MHz operation
    • ? Supports 32-bit interface at 125-MHz operation
    • ? Integrated PHY includes transmitter, receiver, PLL, digital core, and ESD
  • PCIe 3.1 Serdes PHY IP, Silicon Proven in TSMC 40LP
    • Support PHY interface (PIPE4.3) enables multiple IP sources for USB3 MAC layer
    • Supports 5.0Gbps and 10Gbps serial data transmission rate Supports 16-bit or 32-bit parallel interface Data and clock recovery from serial stream
    • Support 8b/10b encoder/decoder(5Gbps), 128/130 encoder/decoder(BGbps) and error indication
    • Tunable receiver detection to detect worse case cables
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