IP Catalog > PCI Expess

PCI Expess IP

Filter
Filter

Login required.

Sign in

Login required.

Sign in

Login required.

Sign in

Search (736)
Compare 736 IP from 36 vendors (1 - 10)
  • PCI Express Verification IP
    • Supports PCI Express specs 1.0/2.0/2.1/3.0/4.0/5.0/6.0
    • Supports mPCIe
    • Supports PIPE, PCS/PMA, Message Bus and SERDES interface
    • Supports MPHY RMMI and serial interface
    Block Diagram -- PCI Express Verification IP
  • PCI Express Synthesizable Transactor
    • Supports PCI Express specs 1.0/2.0/3.0/4.0/5.0/6.0.
    • Supports MPCIE
    • Supports PIPE, PCS/PMA, and serdes interface
    • Supports MPHY RMMI and serial Interface
    Block Diagram -- PCI Express Synthesizable Transactor
  • PCI Express to AMBA 4 AXI/3 AXI Bridge
    • Complete IP solution consists of digital controllers, PHYs and verification IP
    • Fully supports the Synopsys Controller IP for PCI Express Endpoint, Root Port, Dual Mode (EP/RP), and Switch port types
    • Fully compliant with the AMBA 3 AXI and 4 AXI interconnects
    • Full protocol mapping from PCI Express to the AMBA 3 AXI or 4 AXI bus protocol
    Block Diagram -- PCI Express to AMBA 4 AXI/3 AXI Bridge
  • Multi-Port Switch IP for PCI Express
    • Designed according to the PCI Express 4.0, 3.1, 2.1, and 1.1 specifications, including the latest errata
    • Designed according to the PCI-SIG Single-Root I/O Virtualization specification
    • Supports PIPE PHY interface definition including variable clock and variable data
    • Supports 16.0, 8.0, 5.0 and 2.5 Gbps line rates
    Block Diagram -- Multi-Port Switch IP for PCI Express
  • IDE Security IP Modules for PCI Express 7.0
    • Full support of PCI Express 7.0 (64GT/s) IDE specification
    • High-performance AES-GCM based packet encryption, decryption, authentication
    • Seamless integration with Synopsys controllers via TLP/FLIT packet-based interface
    • FLIT mode support
    • Support for PCIe 7.0, 6.0, 5.0, 4.0 and 3.1 data rates
    Block Diagram -- IDE Security IP Modules for PCI Express 7.0
  • Controller IP for PCI Express 7.0
    • Supports all required features of the PCI Express 7.0 (128 GT/s) specification
    • Allows a full 128GT/s x16 lane bandwidth with up to 1024-bit data path implementations
    • Supports advanced RAS data protection features including ECC
    • Advanced RAS-DES features for simplified bring-up and debug
    Block Diagram -- Controller IP for PCI Express 7.0
  • PCI Express 4.0 PHY
    • Compiles with PCIe 4.0, 3.1, 2.1, 1.1 and PIPE 4.4.1 specifications
    • Supports all power-saving modes (P0, P0s, P1, P2) as defined in PIPE 4.4.1 specifications
    • Supports L1 PM/CPM substates with CLKREQ#
    • Supports the separate REFCLK Independent SSC (SRIS) architecture
    Block Diagram -- PCI Express 4.0 PHY
  • PCI Express - Configurable PCI Express 4.0 IP
    • Compliant with "PCI Express™ Base Specification, Rev. 4.0 Version 1.0"
    • Compliant with "PHY Interface For the PCI Express, SATA, and USB3.1 Architectures"
    Block Diagram -- PCI Express - Configurable PCI Express 4.0 IP
  • PCI Express Gen 4 PHY
    • Support 16GT 8GT 5GT 2.5GT data rate
    • Compliant with PCI Express 4.0, 3.1, 2.1, 1.1 and PIPE 4.2 standards
    • x1, x2, x4, x8, x16 lane configuration with bifurcation
    • Multi-tap adaptive programmable continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE)
  • PCI Express Gen 1/2/3/4 Phy
    • TSMC advanced 16 nm FFC CMOS process
    • Available in 1X, 4X, 8X, and 16X configuration
    Block Diagram -- PCI Express Gen 1/2/3/4 Phy
×
Semiconductor IP