Octal spi IP

Implements a controller for a single-, dual-, quad-, or octal-lane Serial Peripheral Interface (SPI) bus, which can operate either as a master or as a slave.
Designed to work with a wide variety of SPI bus variants, the core supports run-time control of several SPI protocol parameters.

Follows Octal SPI basic specification as defined in Macronix (CMOS MXSMIO®(SERIAL MULTI I/O) Flash memory).
Supports Master and Slave Mode.
Supports Serial Peripheral Interface -- Mode 0
Supports below Protocol modes

The Octa SPI Controller and PHY IP supports the fastest access frequency of 200MHz, with DDR Mode and Double Transfer Rate (DTR) Protocol enabling data transfer rates up to 400Mbps with reduced read latency, including support for Octal DDR protocol with DQS for Octal SPI devices.

This controller supports AP Memory’s Xccela open standard Bus for digital interconnect and data communications, suitable for non-volatile and volatile memories such as PSRAM.
This controller enables smooth integration AP memory’s of Xccela PSRAM memory chips into various new-gen devices made with mobile and wearable low power SoCs’.
This memory controller implementation is designed to give the user full flexibility for driving the memory control signals and timing adjustment for data sampling.

The Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, usually an industry-standard FLASH or PSRAM memory device.
In Software Mode, an AHB Master may access the register interface of the Controller to implement a wide range of protocol variants and/or commands on the SPI bus.

Flexibility: Multiple SPI protocol support within single IP
Simplicity: PHY-less IoT operation, or soft storage combo PHY IP simplifies SoC timing
High Performance: Supports maximum Quad SPI / Octal SPI data rates and XIP (Execute In Place)

Octal SPI IP