With growing demand for flash memory in automotive, IoT, and consumer applications, the Host Controller IP for xSPI offers up to eight flash Serial Peripheral Interfaces (i.e., Octal SPI, HyperFlash, xSPI) to further increase the Serial Flash Memory throughput while providing backwards compatibility with single, dual, and quad SPI interfaces.
Host controller IP for controlling flash and other devices on the SPI bus: Quad SPI, Octal SPI, and xSPI
Overview
Key Features
- Supports JEDEC SFDP
- Serial Function Discoverable Parameters allow boot from unknown devices
- All-Digital Storage Combo PHY IP
- Accurate data sampling training, eliminates the need for high-speed clock for SPI interface
- Memory Mapped
- Enables either boot or XIP functionality
- Support for Multi-CMD Channels
Technical Specifications
Related IPs
- Enhanced SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus. Supports eSPI Master & Slave and SPI Master & Slave functions
- Master and Slave SPI Bus Controller
- Quad SPI Flash Memory Controller
- SPI Controller IP- Master/Slave, Parameterized FIFO, AMBA APB / AHB / AXI Bus
- Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support
- QSPI FLASH Controller – XIP functionality (SINGLE, DUAL and QUAD SPI Bus Controller with Double Data Rate support)