With growing demand for flash memory in automotive, IoT, and consumer applications, the Host Controller IP for xSPI offers up to eight flash Serial Peripheral Interfaces (i.e., Octal SPI, HyperFlash, xSPI) to further increase the Serial Flash Memory throughput while providing backwards compatibility with single, dual, and quad SPI interfaces.
Host controller IP for controlling flash and other devices on the SPI bus: Quad SPI, Octal SPI, and xSPI
Overview
Key Features
- Supports JEDEC SFDP
- Serial Function Discoverable Parameters allow boot from unknown devices
- All-Digital Storage Combo PHY IP
- Accurate data sampling training, eliminates the need for high-speed clock for SPI interface
- Memory Mapped
- Enables either boot or XIP functionality
- Support for Multi-CMD Channels
Benefits
- Flexibility: Multiple SPI protocol support within single IP
- Simplicity: PHY-less IoT operation, or soft storage combo PHY IP simplifies SoC timing
- High Performance: Supports maximum Quad SPI / Octal SPI data rates and XIP (Execute In Place)
Technical Specifications
Related IPs
- Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support
- QSPI FLASH Controller – XIP functionality (SINGLE, DUAL and QUAD SPI Bus Controller with Double Data Rate support)
- SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL and QUAD SPI Bus Controller with DDR / DTR support and optional AES Encryption)
- FSPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support)
- Octal SPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support) and DMA Support
- Single, Dual and Quad SPI Flash Controller with Boot and Execute On-The-Fly Features