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Multi-Protocol PMA IP

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Search (22)
Compare 22 IP from 8 vendors (1 - 10)
  • Multiprotocol SerDes PMA
    • Supports over 30 protocols including CEI 6G & 11G SR, MR, LR, Ethernet 10GBASE-X/S/K/R, PCIe Gen1/2/3/4, V-by-One HS/US, CPRI, PON, OTN/OTU, 3GSDI, JESD204A/B/C, SATA1-3, XAUI, SGMII
    • Programmable (De)Serialization width: 8, 10, 16, 20, 32, or 40 bit
    • Tx ring PLL includes fractional multiplication, spread spectrum and Jitter Cleaner function for Sync-E and OTU
    • Core-voltage line driver with programmable pre-and post-emphasis
    Block Diagram -- Multiprotocol SerDes PMA
  • 32G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 22nm
    • Supports data rates of 2.5 to 32 Gbps
    • Optimized for low-power operation and north/south die-edge placement
    • AC-coupled RX front end with on-chip capacitors
    • Flexible ASIC interface for sharing impedance codes among multiple PMA hard macros and reducing the number of external reference resistors for impedance calibration
  • 10Gbps Multi-Protocol PHY IP (+PCIe 3.1)
    • Supports 10G-KR, PCIe 3.1/2.0/1.0, XAUI, Q/SGMII, and Gigabit Ethernet 
    • LC tank PLL with a wide range of reference clock frequencies and SSC 
    • High-performance decision feedback equalization and adaptive CTLE 
    • Serial and parallel loop-back functions 
    • Available in X1 through X10 lane configurations 
    Block Diagram -- 10Gbps Multi-Protocol PHY IP (+PCIe 3.1)
  • 16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
    • Support PCIe G1 to G4 with PCS soft-macro supporting PIPE 4.4.1
    • Support xPON applications: Sym/Asym GPON, Sym/Asym 10GPON, Sym EPON, Sym/Asym 10GEPON
    Block Diagram -- 16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
  • 10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
    • Supports USB 3.1, PCIe 3.0/2.0/1.0, DP-TX v1.4/ eDP-TX v1.4b, SATA 3, 10G-KR and SGMII
    • Supports PCIe L1 sub-states
    • Supports SRIS and internal SSC generation
    • Supports internal and external clock sources with clock active detection
    Block Diagram -- 10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
  • Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 65GP
    • Configurable parallel data widths of 8 / 16 / 32 –bit
    • Input reference 125MHz to support 2.5/5/10G data rates & 100MHz to support 2.5/5/8/16G data rates
    • Tight control over termination resistor (~50 Ohm) with on chip calibration
    • Tight skew control of 1UI between lanes of the PMA
  • Multi-Link Multi-Protocol SerDes 10Gbps in TSMC 55LP
    • Configurable parallel data widths of 8 / 16 / 32 –bit
    • Input reference 125MHz to support 2.5/5/10G data rates & 100MHz to support 2.5/5/8/16G data rates
    • Tight control over termination resistor (~50 Ohm) with on chip calibration
    • Tight skew control of 1UI between lanes of the PMA
  • Multi-Link Multi-Protocol SerDes 10Gbps in GF 28SLP
    • Configurable parallel data widths of 8 / 16 / 32 –bit
    • Input reference 125MHz to support 2.5/5/10G data rates & 100MHz to support 2.5/5/8/16G data rates
  • Multi-Link Multi-Protocol SerDes 16Gbps in TSMC 28HPC
    • Supports channel with 15dB at 5.275Ghz/10.55Gbps and BER <10-17
    • Built in self test (BIST) through Feedback path from Transmitter and Receiver ports.
  • Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
    • Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
    • Compact form factor – 0.116 mm2 active silicon area per lane including ESD
    • Industry leading low power – typically 6.3 mW/Gbps (@6Gbps) including termination
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    Block Diagram -- Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
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