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MSC IP

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  • Multichannel Sound Controller
    • Multichannel sound controller for consumer electronics applications
    • Support S/PDIF and 4-channel I2S interfaces
    • Sound buffers of arbitrary size in external memory
    • Relaxed requirements for interrupt handling
  • DAB modulator
    • Fully compliant with ETSI EN 300 401 V1.4.1 2006-06, for DAB
    • DAB-Modes: I, II, III, IV
    • All protection levels supported
    • Synchronous design
  • Scaler IP - MSCALE
    • Silicon Proven Several Times for Mobile Phone
    • Use Small Gate Counts
    • Optimized for Power Saving
    Block Diagram -- Scaler IP - MSCALE
  • cjTAG IEEE 1149.7 DTS Adapter
    • IEEE 1149.1 interface to existing test/debug hardware
    • IEEE 1149.7 interface to target system(s)
    • Supports all IEEE 1149.7 scan formats
    • Supports all IEEE 1149.7 scan topologies
    Block Diagram -- cjTAG IEEE 1149.7 DTS Adapter
  • cjTAG IEEE 1149.7 Compact TAP Controller
    • Supports IEEE 1149.7 classes 0–5 (selected through hardware configuration parameter)
    • Partitioned along IEEE 1149.7-specified functional boundaries (so that only the required hardware is included):
    • Supports all mandatory and optional scan formats: JScan0–3, SScan0–3, OScan0–7, and MScan
    • Supports all mandatory and optional cJTAG commands
    Block Diagram -- cjTAG IEEE 1149.7 Compact TAP Controller
  • IEEE 1149.7 DTS Adapter IP
    • Compliant with IEEE 1149.7 standard specification.
    • Full IEEE 1149.7 DTS Adapter functionality.
    • Supports IEEE 1149.7 classes T0 to T5.
    • Supports Reset and Escape sequences generation of TAP controller.
  • IEEE 1149.7 Compact TAP IP
    • Compliant with IEEE 1149.7 standard specification.
    • Supports TAP.7 capability classes T0 to T5.
    • Supports Reset and Selection Unit (RSU) for class T0 optional features.
    • Supports Extended Protocol Unit (EPU) for classes T0 to T3.
  • IEEE 802.15.3c Irregular LDPC(672,336), LDPC(672,504), LDPC(672,588) encoder and decoder
    • Belief-propagation iterative decoding
    • Pipeline design, 4 clocks perdecoding iteration
    • Single clock synchronous design; registered inputs and outputs;
    • Single-port memories only
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