CJTAG (IEEE 1149.7) Verification IP

Overview

CJTAG (IEEE 1149.7) Verification IP provides an smart way to verify the CJTAG (IEEE 1149.7) component of a SOC or a ASIC. The SmartDV's CJTAG (IEEE 1149.7) Verification IP is fully compliant with standard CJTAG (IEEE 1149.7) Standard and provides the following features.

CJTAG (IEEE 1149.7) Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

CJTAG (IEEE 1149.7) Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Key Features

Fully compatible with IEEE 1149.7 standard.
Can be used as TAP controller (slave) or TAP instruction/data generator (Master) for CJTAG.
Comes with CJTAG monitor to check and report any protocol violation.
Supports TAP.7 capability classes T0 to T5
Supports Extended Protocol Unit (EPU) for classes 0 to 3
Supports all mandatory and optional EPU commands
Supports Advanced Protocol Unit (APU) for classes 4 and 5
Supports 4 and 2 pin interface as specified in CJTAG (IEEE 1149.7)
Supports all mandatory and optional scan formats (JScan, MScan, OScan, and SScan)
CJTAG (IEEE 1149.7) supports following scan terminology
- Data Register Scan
- Instruction Register Scan
- Control Register Scan
- Zero-Bit Scan
Can be extended with user defines instructions and registers.
Supports optional reset signal.
On-the-fly protocol and data checking.
Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
Built in functional coverage analysis.
Callbacks support for BFM and Monitor.
Status counters for various events on bus.
CJTAG Verification IP comes with complete test suite to test every feature of CJTAG (IEEE 1149.7) specification.

Benefits

Faster testbench development and more complete verification of CJTAG (IEEE 1149.7) designs.
Easy to use command interface simplifies testbench control and configuration.
Simplifies results analysis.
Runs in every major simulation environment.

Block Diagram

Deliverables

Complete regression suite containing all the CJTAG (IEEE 1149.7) testcases.
Examples showing how to connect various components and usage of BFM and Monitor.
Detailed documentation of all classes, tasks and functions used in verification env.
Documentation also contains User's Guide and Release notes.

Technical Specifications

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