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MPEG IP

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Search (93)
Compare 93 IP from 33 vendors (1 - 10)
  • ETR101290 IP core (Checks MPEG TS stream conformity to ETSI TR 101 290 V1.4.1 (2020-06))
    • Checks MPEG TS stream conformity to ETSI TR 101 290 V1.4.1 (2020-06)
    Block Diagram -- ETR101290 IP core (Checks MPEG TS stream conformity to ETSI TR 101 290 V1.4.1 (2020-06))
  • MPEG TS Deserializer
    • Drop-in module for Xilinx Spartan-6, Virtex-6, Artix-7, Kintex-7, Virtex-7, Zynq FPGAs
    • Full synthesizable RTL VHDL design (not delivered) for easy customization
    Block Diagram -- MPEG TS Deserializer
  • MPEG TS Serializer
    • Drop-in module for Xilinx Spartan-6, Virtex-6, Artix-7, Kintex-7, Virtex-7, Zynq FPGAs
    • Full synthesizable RTL VHDL design (not delivered) for easy customization
    Block Diagram -- MPEG TS Serializer
  • MPEG Transport Stream Multiplexing & Encapsulation Engine
    • The MTS-E core multiplexes and encapsulates audio, video, and metadata streams in a single MPEG Transport Stream (MTS), and optionally encapsulates the TS packets in Real-Time Transport Protocol (RTP) packets.
    • Under its default configuration, the MTS-E multiplexing and encapsulation engine supports two input stream channels, e.g., one Audio and one Video.
    Block Diagram -- MPEG Transport Stream Multiplexing & Encapsulation Engine
  • Rx MPEG TS Interface
    • De-buffering and de-jittering MPEG-TS packets
    • Single clock (125MHz or higher)
    • Supports CBR input streams only (a BYPASS mode is available for VBR input streams)
    • Supports 188, 204 or 208 bytes packet input
    Block Diagram -- Rx MPEG TS Interface
  • MPEG2TS Verification IP
    • Full MPEG-2 TS Transmitter and Receiver functionality.
    • Supports the combination of the video and audio coding methods defined in Parts 2 and 3 of ISO/IEC 13818
    • Supports Generic coding of moving pictures and associated audio information Part 7 Advanced Audio Coding (AAC).
    • Supports Generic coding of moving pictures and associated audio information for Systems as per ISO/IEC 13818-1
    Block Diagram -- MPEG2TS Verification IP
  • MPEG2 ENCODER IIP
    • Supports MPEG-2 standard specification.
    • Supports full MPEG-2 encoder functionality.
    • Supports video resolution up to 1920x1080@60fps.
    • Supports input bit rates up to 100Mbps.
    Block Diagram -- MPEG2 ENCODER IIP
  • MPEG2 DECODER IIP
    • Supports MPEG-2 standard specification.
    • Supports full MPEG-2 decoder functionality.
    • Supports video resolution up to 1920x1080@60fps.
    • Supports input bit rates up to 100Mbps.
    Block Diagram -- MPEG2 DECODER IIP
  • MPEG4 ENCODER IIP
    • Supports MPEG-4 standard specification.
    • Supports full MPEG-4 encoder functionality.
    • Supports YUV 4:2:2 interleaved data as an input.
    • Supports image width/height as multiple of 16.
    Block Diagram -- MPEG4 ENCODER IIP
  • MPEG4 DECODER IIP
    • Supports MPEG-4 standard specification.
    • Supports full MPEG-4 decoder functionality.
    • Supports YUV 4:2:2 interleaved data as an input
    • Supports image width as multiple of 16 and height as multiple of 16
    Block Diagram -- MPEG4 DECODER IIP
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