The MVD MPEG TS Deserializer core is a drop-in module that includes the following functions:
• Data acquisition on clock
• Serial/parallel Conversion
• Auto adaptation to 188/204 bytes packet Input
• 188 bytes MPEG-TS output
• No decoding control
MPEG TS Deserializer
Overview
Key Features
- Drop-in module for Xilinx Spartan-6, Virtex-6, Artix-7, Kintex-7, Virtex-7, Zynq FPGAs
- Full synthesizable RTL VHDL design (not delivered) for easy customization
Block Diagram
Applications
- MVD MPEG TS Deserializer may be used in applications related to DVB/MPEG transport streams for Satellite tuner data de-serialization.
Deliverables
- Datasheet
- Netlist for core generation
- VHDL top file
- VHDL source code : can be delivered as an option under NDA and other specific clauses
Technical Specifications
Availability
Available
Related IPs
- Rx MPEG TS Interface
- MPEG TS Serializer
- ETR101290 IP core (Checks MPEG TS stream conformity to ETSI TR 101 290 V1.4.1 (2020-06))
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- Sub-LVDS receiver followed by 1:4 de-serializer
- Deserializer 1:32 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain