MIPI I3C Basic Secondary Controller IP
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MIPI I3C Basic Secondary Controller
- The I3C-SC core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Secondary Controller core compliant with the latest MIPI I3C BasicSM specification.
- As a secondary controller, the I3C-SC can act either as a bus target or a bus controller. Compliant to the I3C Basic specification, the core communicates in Single Data Rate (SDR) mode but can tolerate High Data Rate (HDR) traffic
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MIPI I3C v1.1.1 Basic Controller and Target
- Supports MIPI I3C v1.1.1 specification
- Compliant with MIPI I3C Conformance Test Suite (CTS) v1.0
- Supports the MIPI I3C Host Controller Interface and DDR5 JEDEC JESD403-1 and System Management MCTP specifications
- Supports SDR, HDR-DDR, HDR-TSL/TSP; all data rates up to 33.4 Mbps
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MIPI I3C v1.1.1 Basic Target lite
- Supports MIPI I3C v1.1.1 specification
- Compliant with MIPI I3C Conformance Test Suite (CTS) v1.0
- Supports the MIPI I3C Host Controller Interface and DDR5 JEDEC JESD403-1 and System Management MCTP specifications
- Supports SDR, HDR-DDR, HDR-TSL/TSP; all data rates up to 33.4 Mbps
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I3C Controller IP – Master / Slave, Parameterized FIFO, APB Bus. I3C Basic Specification Design
- Master / Slave MIPI I3C Controller
- Supports following I3C bus speeds: Single Data Rate (SDR) - up to 12.5 MHz
- I3C Communications Support: I3C SDR / Broadcast / Direct Messages; Legacy I2C Message
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Simulation VIP for MIPI I3C
- I3C SDR Mode
- SDR private read/write data transfers
- I3C HDR-DDR Mode
- HDR-DDR enter and exit patterns, command coding, bus turnaround, DDR Flow Control Elements and error detection