IP Catalog > Interface IP > Interconnect IP > MIPI IP > MIPI Controller IP > MIPI I3C IP > Simulation VIP for MIPI I3C

Simulation VIP for MIPI I3C

Overview

In production since 2015 on dozens of production design.

The Cadence® Verification IP (VIP) for MIPI® I3Csm VIP provides support for the MIPI I3C protocol specification. It provides a mature, highly capable compliance verification solution that supports simulation, protocol checking, coverage collection, and analysis, making it applicable to intellectual property (IP), system-on-chip (SoC), and system-level verification. The VIP for I3C helps you reduce time to test, accelerate verification closure, and ensure end-product quality. The VIP runs on all major simulators and supports SystemVerilog and e verification languages along with associated methodologies, including the Universal Verification Methodology (UVM) and Open Verification Methodology (OVM).

The I3C Specification describes the I3C interface (Improved Inter Integrated Circuit), which is used for easing sensor system design architectures by providing a fast, low-cost, low-power, two-wire digital interface for sensors.

Supported Specifications: MIPI I3C specification v1.0, v1.1, and v1.01. MIPI I3C Basic specification v1.0 and I2C specification.

Key Features

  • I3C SDR Mode
    • SDR private read/write data transfers
  • I3C HDR-DDR Mode
    • HDR-DDR enter and exit patterns, command coding, bus turnaround, DDR Flow Control Elements and error detection
  • I3C HDR-Ternary Modes
    • Supports HDR-TSP and HDR-TSL modes including Data Transfer Ending Procedure Control (ENDXFER) and Ternary Flow Control Elements
  • I2C Legacy Mode
    • Supports I2C-only mode to simulate the I2C protocol as defined in the I2C specification
  • I3C CCC
    • Mandatory and optional CCCs: Direct and broadcast commands
  • Secondary Controller
    • Supports processing Secondary Controller controller role requests
  • Target Agents
    • Supports any number of I3C and I2C targets up to the limit of the specification
  • In-Band Interrupt
    • Supports processing of In-Band Interrupts from I3C targets
  • In-Band Hard Reset
    • Supports processing of In-Band Hard Reset
  • Arbitration
    • Supports I3C address arbitration
  • Hot Join
    • Supports hot-join procedure for adding targets to the bus on the fly
  • Dynamic Address Assignment
    • Supports the mandatory dynamic address assignment mode including SETDASA, SETAASA (v1.01 feature).
  • SDR Error Detection and Recovery
    • Supports SDR error detection and recovery methods for I3C Controller and I3C Target devices, including S0 error detection and S0/S1 error recovery mechanism
  • Target Response Control
    • Implements user control of target response fields such as data, target busy, target sending NACK, etc.
  • I2C 50ns Glitch Filter
    • Supports optional 50ns glitch filter for I2C devices
  • I2C Clock Stretching
    • Supports I2C stretching
  • I2C Start Byte
    • Sending of optional start byte in transactions is available
  • I2C Speed Modes
    • Standard, Fast, Fast Plus, Ultra Fast, and High Speed
  • I2C 7-bit/10-bit Addressing
    • Configurable option to use for target addressing
  • I2C Multi Manager
    • Supports I2C multi manager feature
  • Group Addressing
    • Supports this feature where Controller can send transaction on multiple targets at the same time using Group Addressing
  • Target Reset
    • Supports new target reset pattern introduce in V1.1
  • Monitoring Device Early Termination Capability
    • Supports feature where target which is not participating in transaction can terminate the transaction
  • Device to Device Tunneling
    • Supports target to target transfer
  • HDR Bulk Transport Mode
    • Supports HDR BT Mode where bulk transfer of data can be done
  • Multi lane Data Transfer
    • Supports multi lane for SDR, HDR DDR, HDR BT modes, multi lane for HDR TSP is under development

    Block Diagram

    Simulation VIP for MIPI I3C Block Diagram

    Technical Specifications

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